公开(公告)号：US20090154542A1

公开(公告)日：2009-06-18

申请号：US12002539

申请日：2007-12-17

申请人： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Shumarayev

发明人： Weiqi Ding ,  Mengchi Liu ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03H7/30

CPC分类号： H04L25/03885 ,  H04L7/0054 ,  H04L25/03019 ,  H04L25/03878

摘要： Circuitry for receiving a high-speed serial data signal (e.g., having a bit rate in the range of about 10 Gpbs and higher) includes a two-stage, continuous-time, linear equalizer having only two serially connected stages. Phase detector circuitry may be provided for receiving the serial output of the equalizer and for converting successive pairs of bits in that output to successive parallel-form bit pairs. Further demultiplexing circuitry may be provided to demultiplex successive groups of the parallel-form bit pairs to final groups of parallel bits, which can be quite large in terms of number of bits (e.g., 64 parallel bits). Another aspect of the invention relates to multiplexer circuitry for efficiently going in the opposite direction from such relatively large groups of parallel data bits to a high-speed serial data output signal.

摘要翻译： 用于接收高速串行数据信号（例如，具有在约10Gpbs及更高的范围内的比特率）的电路包括仅具有两个串联连接级的两级连续时间线性均衡器。 可以提供相位检测器电路用于接收均衡器的串行输出，并将该输出中的连续比特对转换为连续并行形式的位对。 可以提供进一步的解复用电路以将并行形式位对的连续组分解成最终并行位组，在位数（例如，64个并行位）方面可能相当大。 本发明的另一方面涉及用于从相对大的并行数据比特组相对于高速串行数据输出信号有效地进行反向的多路复用器电路。

公开(公告)号：US20090011716A1

公开(公告)日：2009-01-08

申请号：US11773234

申请日：2007-07-03

申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H04Q7/20

CPC分类号： H04L25/45

摘要： A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

摘要翻译： 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US07460040B1

公开(公告)日：2008-12-02

申请号：US11754670

申请日：2007-05-29

申请人： Thungoc M. Tran ,  Yu Xu ,  Kwong-Wen Wei ,  Sergey Shumarayev

发明人： Thungoc M. Tran ,  Yu Xu ,  Kwong-Wen Wei ,  Sergey Shumarayev

IPC分类号： H03M9/00

CPC分类号： H03M9/00 ,  H03K5/135 ,  H03K19/1774 ,  H03K19/17744

摘要： A high-speed serial interface for a programmable logic device includes a plurality of features to handle the various issues that may arise with data rates over 1 Gbps and particularly over 1.25 Gbps. Those features may include dynamic phase alignment to control clock-data skew, data realignment (e.g., bit slip circuitry) to account for channel-to-channel skew, full-duplex serializer and deserializer, out-of-range frequency support for low frequencies, and a soft-CDR mode.

摘要翻译： 用于可编程逻辑器件的高速串行接口包括多个特征，以处理在1Gbps，特别是超过1.25Gbps的数据速率下可能出现的各种问题。 这些特征可以包括动态相位对准以控制时钟数据偏移，数据重新对准（例如位移电路）以解决通道间通道偏移，全双工串行器和解串器，超低频率频率支持 ，和软CDR模式。

公开(公告)号：US07429897B1

公开(公告)日：2008-09-30

申请号：US11514489

申请日：2006-08-31

申请人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

发明人： Tim Tri Hoang ,  Sergey Shumarayev ,  Wilson Wong

IPC分类号： H03B5/08

CPC分类号： H03K3/0315 ,  H03K5/133 ,  H03K2005/00202 ,  H03L7/0995 ,  H03L2207/06

摘要： Voltage controlled oscillator (VCO) circuitry with low phase noise and a wide range of operating frequencies is presented. The VCO circuitry includes circuitry with two or more VCO sub-circuits, each sub-circuit being optimized to produce output clock signals with low phase noise and with frequencies in a different range. Sub-circuits with gear inputs may be operative to produce output clock signals in a lower range of frequencies, while sub-circuits optimized for high speed operation may be used to produce output signals in a higher range of frequencies. A control circuit may be used to produce a control signal coupled to all sub-circuits. The control signal may set the operating frequency of the sub-circuits.

摘要翻译： 介绍了具有低相位噪声和宽范围工作频率的压控振荡器（VCO）电路。 VCO电路包括具有两个或多个VCO子电路的电路，每个子电路被优化以产生具有低相位噪声和频率在不同范围内的输出时钟信号。 具有齿轮输入的子电路可以用于产生在较低频率范围内的输出时钟信号，而针对高速操作优化的子电路可用于产生较高频率范围内的输出信号。 控制电路可用于产生耦合到所有子电路的控制信号。 控制信号可以设定子电路的工作频率。

公开(公告)号：US07358883B1

公开(公告)日：2008-04-15

申请号：US11470343

申请日：2006-09-06

申请人： Tin H. Lai ,  Wilson Wong ,  Sergey Shumarayev

发明人： Tin H. Lai ,  Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03M1/66

CPC分类号： G11C7/12 ,  G11C7/1045 ,  H03M1/662

摘要： A bias circuit includes a digital to analog converter (D2A) generating an output representing a voltage level for tuning an analog signal. The D2A is coupled to a primary register frame that includes a plurality of register frames that are serially linked. The bias circuit includes a decoder also coupled to the primary register frame. An output enable logic module is also included. The output enable logic module determines when the primary register has a complete data set as the data is shifted into the primary register frame from a memory region that may be a ROM, RAM, soft IP of a PLD, an intelligent host or tester serial data input stream. A method for adjusting a signal through a bias circuit is also provided.

摘要翻译： 偏置电路包括产生表示用于调谐模拟信号的电压电平的输出的数模转换器（D2A）。 D2A耦合到包括多个串行连接的寄存器帧的主寄存器帧。 偏置电路包括还耦合到主寄存器框架的解码器。 还包括一个输出使能逻辑模块。 输出使能逻辑模块确定主寄存器何时具有完整数据集，因为数据从可能是ROM，RAM，PLD的软IP，智能主机或测试仪串行数据的存储器区域移入主寄存器帧 输入流。 还提供了一种通过偏置电路调整信号的方法。

公开(公告)号：US07245144B1

公开(公告)日：2007-07-17

申请号：US11169242

申请日：2005-06-27

申请人： Wilson Wong ,  Sergey Shumarayev

发明人： Wilson Wong ,  Sergey Shumarayev

IPC分类号： H03K17/16

CPC分类号： H03K19/018564 ,  H03F3/45928 ,  H03F2203/45078 ,  H03F2203/45082 ,  H03F2203/45101 ,  H03F2203/45134 ,  H03F2203/45138 ,  H03F2203/45154 ,  H03F2203/45222 ,  H03F2203/45541 ,  H03F2203/45566 ,  H03F2203/45626 ,  H03F2203/45681 ,  H03F2203/45686

摘要： Systems and methods are provided using common-mode-voltage bias circuitry to make common-mode-voltage adjustments to differential driver circuitry in integrated circuit differential communications links. Adjustable bias circuitry may be controlled using static and dynamic control signals. Dynamic control signals can be produced by core logic on a programmable logic device or other integrated circuit. Static control signals can be produced by programmable elements. Bias circuit adjustments made at one end of a differential link can be used to improve performance at either end of the link or can be used to improve power consumption or to balance power and performance considerations. The same integrated circuit design can be used in both AC-coupled and DC-coupled environments. The bias circuitry can be formed from an adjustable current source and adjustable resistor. The current source and adjustable resistors can be controlled by the same control signals.

摘要翻译： 使用共模电压偏置电路提供系统和方法，以对集成电路差分通信链路中的差分驱动器电路进行共模电压调整。 可调节的偏置电路可以使用静态和动态控制信号来控制。 动态控制信号可以由可编程逻辑器件或其他集成电路上的核心逻辑产生。 静态控制信号可以由可编程元件产生。 差分链路一端进行的偏置电路调整可用于提高链路两端的性能，或者可用于提高功耗或平衡功率和性能考虑。 同样的集成电路设计可用于交流耦合和直流耦合环境。 偏置电路可以由可调电流源和可调电阻器形成。 电流源和可调电阻可由相同的控制信号控制。

公开(公告)号：US20070014344A1

公开(公告)日：2007-01-18

申请号：US11182658

申请日：2005-07-14

申请人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

发明人： Simardeep Maangat ,  Sergey Shumarayev ,  Wilson Wong ,  ThuNgoc Tran

IPC分类号： H03H7/30

CPC分类号： H04L25/03885 ,  H04B3/04 ,  H04L25/03019

摘要： Data signals transmitted over transmission media suffer from attenuation caused by the transmission media. Equalization circuitry may be provided to compensate for attenuation caused by the transmission media. Equalization circuitry may include multiple stages arranged in series to allow the frequency responses of the stages to aggregate together. Each stage may be programmable to insert a zero, which causes the frequency response of the stage to increase in magnitude by 20 dB/decade. The frequency location of the zero may also be programmable to allow each stage to contribute a certain amount of gain for a specific frequency. Each stage may also be programmable to determine the location of poles for reduction of high frequency noise and cross-talk cancellation.

摘要翻译： 通过传输介质传输的数据信号遭受由传输介质引起的衰减。 可以提供均衡电路以补偿由传输介质引起的衰减。 均衡电路可以包括串联布置的多个级，以允许级的频率响应聚合在一起。 每个级可以是可编程的，以插入一个零，这使得该级的频率响应在幅度上增加20dB /十倍。 零的频率位置也可以是可编程的，以允许每个级对特定频率贡献一定量的增益。 每个阶段也可以被编程以确定用于降低高频噪声和串扰取消的极点的位置。

公开(公告)号：US20060119382A1

公开(公告)日：2006-06-08

申请号：US11006420

申请日：2004-12-07

申请人： Sergey Shumarayev ,  Rakesh Patel

发明人： Sergey Shumarayev ,  Rakesh Patel

IPC分类号： H03K19/003

CPC分类号： H03K19/0016 ,  G06F17/5054 ,  G06F2217/84 ,  H01L2924/0002 ,  H03K19/00369 ,  H03K19/17732 ,  H03K19/17748 ,  H03K19/17784 ,  H03K19/17792 ,  H01L2924/00

摘要： A programmable logic device (PLD) includes a circuit that controls a supply voltage of at least a portion of the circuitry within the PLD (such as a block, a sub-block, or a region). The circuit also filters noise within the PLD. Controlling the supply voltage allows trading off various performance characteristics, such as speed and power consumption.

摘要翻译： 可编程逻辑器件（PLD）包括控制PLD（例如块，子块或区域）内的电路的至少一部分的电源电压的电路。 该电路还对PLD内的噪声进行滤波。 控制电源电压可以消除各种性能特性，如速度和功耗。

公开(公告)号：US06989689B2

公开(公告)日：2006-01-24

申请号：US10852858

申请日：2004-05-24

申请人： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

发明人： Tony Ngai ,  Bruce Pedersen ,  Sergey Shumarayev ,  James Schleicher ,  Wei-Jen Huang ,  Michael Hutton ,  Victor Maruri ,  Rakesh Patel ,  Peter J. Kazarian ,  Andrew Leaver ,  David W. Mendel ,  Jim Park

IPC分类号： H03K19/177

CPC分类号： G06F7/506 ,  H03K19/1737 ,  H03K19/177 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/17792

摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

公开(公告)号：US06980022B1

公开(公告)日：2005-12-27

申请号：US10946902

申请日：2004-09-21

申请人： Sergey Shumarayev ,  Thomas White

发明人： Sergey Shumarayev ,  Thomas White

IPC分类号： H04L25/02 ,  H03K19/0175

CPC分类号： H04L25/0278 ,  H04L25/0272 ,  H04L25/0284 ,  H04L25/0296 ,  H04L25/0298

摘要： Various embodiments for implementing circuits and systems with highly flexible interface circuitry that is capable of realizing programmable on-chip termination and DC level control. A number of techniques use existing I/O resources to implement programmable on-chip termination and DC level control that enable an integrated circuit to meet a variety of different high speed single-ended and differential I/O standards.

摘要翻译： 用于实现具有高度灵活的接口电路的电路和系统的各种实施例，其能够实现可编程片上终止和DC电平控制。 许多技术使用现有的I / O资源实现可编程片上终止和DC电平控制，使集成电路能够满足各种不同的高速单端和差分I / O标准。