公开(公告)号：US07531207B2

公开(公告)日：2009-05-12

申请号：US10780919

申请日：2004-02-17

申请人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

发明人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

IPC分类号： B05D5/12 ,  C23C16/00

CPC分类号： C23C14/5806 ,  C23C14/086 ,  C23C16/40 ,  C23C16/56

摘要： Methods of forming depositing a ferroelectric thin film, such as PGO, by preparing a substrate with an upper surface of silicon, silicon oxide, or a high-k material, such as hafnium oxide, zirconium oxide, aluminum oxide, and lanthanum oxide, depositing an indium oxide film over the substrate, and then depositing the ferroelectric film using MOCVD.

摘要翻译： 通过制备具有硅，氧化硅或高k材料如氧化铪，氧化锆，氧化铝和氧化镧的上表面的衬底来形成沉积铁电薄膜（例如PGO）的方法，沉积 在衬底上形成氧化铟膜，然后使用MOCVD沉积铁电体膜。

公开(公告)号：US20080280426A1

公开(公告)日：2008-11-13

申请号：US11801210

申请日：2007-05-09

申请人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Douglas J. Tweet ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L29/739 ,  H01L21/20

CPC分类号： C30B29/406 ,  C30B25/183 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02642 ,  H01L21/02647 ,  H01L29/2003 ,  H01L29/267

摘要： A method is provided for forming a matching thermal expansion interface between silicon (Si) and gallium nitride (GaN) films. The method provides a (111) Si substrate and forms a first aluminum (Al)-containing film in compression overlying the Si substrate. Nano-column holes are formed in the first Al-containing film, which exposes regions of the underlying Si substrate. A layer of GaN layer is selectively grown from the exposed regions, covering the first Al-containing film. The GaN is grown using a lateral nanoheteroepitaxy overgrowth (LNEO) process. The above-mentioned processes are reiterated, forming a second Al-containing film in compression, forming nano-column holes in the second Al-containing film, and selectively growing a second GaN layer. Film materials such as Al2O3, Si1-xGex, InP, GaP, GaAs, AlN, AlGaN, or GaN, may be initially grown at a low temperature. By increasing the growth temperatures, a compressed layer of epitaxial GaN can be formed on a Si substrate.

摘要翻译： 提供了一种在硅（Si）和氮化镓（GaN）膜之间形成匹配的热膨胀界面的方法。 该方法提供（111）Si衬底并且在压缩覆盖Si衬底上形成第一含铝（Al）的膜。 在第一含Al膜中形成纳米柱孔，其暴露下面的Si衬底的区域。 从暴露区域选择性地生长GaN层，覆盖第一含Al膜。 使用横向纳米外延生长（LNEO）工艺生长GaN。 重复上述过程，在压缩中形成第二含Al膜，在第二含Al膜中形成纳米柱孔，并选择性地生长第二GaN层。 可以最初在低温下生长诸如Al 2 O 3 3，Si 1-x Ge x，InP，GaP，GaAs，AlN，AlGaN或GaN的膜材料。 通过增加生长温度，可以在Si衬底上形成外延GaN的压缩层。

公开(公告)号：US07379320B2

公开(公告)日：2008-05-27

申请号：US11262117

申请日：2005-10-28

申请人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L21/8247

CPC分类号： H01L27/1159 ,  H01L21/84 ,  H01L27/11502 ,  H01L27/11585

摘要： An MFIS memory array having a plurality of MFIS memory transistors with a word line connecting a plurality of MFIS memory transistor gates, wherein all MFIS memory transistors connected to a common word line have a common source, each transistor drain serves as a bit output, and all MFIS channels along a word line are separated by a P+ region and are further joined to a P+ substrate region on an SOI substrate by a P+ region is provided. Also provided are methods of making an MFIS memory array on an SOI substrate; methods of performing a block erase of one or more word lines, and methods of selectively programming a bit.

摘要翻译： 一种MFIS存储器阵列，具有多个具有连接多个MFIS存储晶体管栅极的字线的MFIS存储晶体管，其中连接到公共字线的所有MFIS存储晶体管具有公共源，每个晶体管漏极用作位输出，以及 沿着字线的所有MFIS通道被P +区隔开，并且通过P +区进一步连接到SOI衬底上的P +衬底区域。 还提供了在SOI衬底上制造MFIS存储器阵列的方法; 执行一个或多个字线的块擦除的方法以及有选择地编程位的方法。

公开(公告)号：US07329548B2

公开(公告)日：2008-02-12

申请号：US11215521

申请日：2005-08-30

申请人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

发明人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

IPC分类号： H01L21/00 ,  H01L21/338 ,  H01L21/8242

CPC分类号： H01L21/28291 ,  H01L29/66583 ,  H01L29/78

摘要： A method of fabricating a conductive metal oxide gate ferroelectric memory transistor includes forming an oxide layer a substrate and removing the oxide layer in a gate area; depositing a conductive metal oxide layer on the oxide layer and on the exposed gate area; depositing a titanium layer on the metal oxide layer; patterning and etching the titanium layer and the metal oxide layer to remove the titanium layer and the metal oxide layer from the substrate except in the gate area; depositing, patterning and etching an oxide layer to form a gate trench; depositing and etching a barrier insulator layer to form a sidewall barrier in the gate trench; removing the titanium layer from the gate area; depositing, smoothing and annealing a ferroelectric layer in the gate trench; depositing, patterning and etching a top electrode; and completing the conductive metal oxide gate ferroelectric memory transistor.

摘要翻译： 一种制造导电金属氧化物栅极铁电存储晶体管的方法，包括：在衬底上形成氧化物层并去除栅极区域中的氧化物层; 在氧化物层和暴露的栅极区上沉积导电金属氧化物层; 在所述金属氧化物层上沉积钛层; 图案化和蚀刻钛层和金属氧化物层以除去栅极区域之外的基板以除去钛层和金属氧化物层; 沉积，图案化和蚀刻氧化物层以形成栅极沟槽; 沉积和蚀刻阻挡绝缘体层以在栅极沟槽中形成侧壁势垒; 从栅极区域去除钛层; 沉积，平滑和退火栅极沟槽中的铁电层; 沉积，图案化和蚀刻顶部电极; 并完成导电金属氧化物栅极铁电存储晶体管。

公开(公告)号：US07320897B2

公开(公告)日：2008-01-22

申请号：US11090386

申请日：2005-03-23

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Wei-Wei Zhuang

IPC分类号： H01L21/66

CPC分类号： H01L33/08 ,  B82Y20/00 ,  H01L33/18 ,  H01L33/24 ,  H01L33/34 ,  H01L33/502 ,  Y10S977/834

摘要： A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.

摘要翻译： 提供了一种纳米末端电致发光（EL）二极管和一种用于制造所述器件的方法。 该方法包括：形成多个Si纳米二极管; 形成覆盖所述纳米二极管的磷光体层; 并且形成覆盖磷光体层的顶部电极。 纳米二极管通过以下方式形成：形成具有顶表面的Si衬底; 形成Si对孔; 形成层叠Si层的厚度为30〜300纳米（nm）的Si的n +层; 形成覆盖在衬底顶表面上的反应离子蚀刻（RIE）诱导的聚合物草; 使用RIE诱导的聚合物草作为掩模，蚀刻未被掩模覆盖的基底的区域; 以及在由掩模覆盖的衬底的区域中形成纳米二极管二极管。

公开(公告)号：US07256465B2

公开(公告)日：2007-08-14

申请号：US10761704

申请日：2004-01-21

申请人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

发明人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce D. Ulrich

IPC分类号： H01L21/336 ,  H01L29/94

CPC分类号： H01L29/66545 ,  H01L29/1054 ,  H01L29/26 ,  H01L29/6659 ,  H01L29/66651 ,  H01L29/7833

摘要： An ultra-shallow surface channel MOS transistor and method for fabricating the same have been provided. The method comprises: forming CMOS source and drain regions, and an intervening well region; depositing a surface channel on the surface overlying the well region; forming a high-k dielectric overlying the surface channel; and, forming a gate electrode overlying the high-k dielectric. Typically, the surface channel is a metal oxide, and may be one of the following materials: indium oxide (In2O3), ZnO, RuO, ITO, or LaX-1SrXCoO3. In some aspects, the method further comprises: depositing a placeholder material overlying the surface channel; and, etching the placeholder material to form a gate region overlying the surface channel. In one aspect, the high-k dielectric is deposited prior to the deposition of the placeholder material. Alternately, the high-k dielectric is deposited following the etching of the placeholder material.

摘要翻译： 提供了一种超浅表面沟道MOS晶体管及其制造方法。 该方法包括：形成CMOS源极和漏极区域以及中间阱区域; 在覆盖所述阱区域的表面上沉积表面通道; 形成覆盖表面通道的高k电介质; 并形成覆盖高k电介质的栅电极。 通常，表面通道是金属氧化物，并且可以是以下材料之一：氧化铟（In 2 O 3），ZnO，RuO，ITO或LaX-1SrXCoO 3。 在一些方面，所述方法还包括：沉积覆盖所述表面通道的占位符材料; 并且蚀刻占位符材料以形成覆盖表面通道的栅极区域。 在一个方面，高k电介质沉积在占位符材料的沉积之前。 或者，在占位符材料的蚀刻之后沉积高k电介质。

公开(公告)号：US07053001B2

公开(公告)日：2006-05-30

申请号：US10676983

申请日：2003-09-30

申请人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce Dale Ulrich

发明人： Tingkai Li ,  Sheng Teng Hsu ,  Bruce Dale Ulrich

IPC分类号： H01I21/302

CPC分类号： H01L21/31122 ,  H01L21/28291 ,  H01L21/2855 ,  H01L21/32051

摘要： A method of selective etching a metal oxide layer for fabrication of a ferroelectric device includes preparing a silicon substrate, including forming an oxide layer thereon; depositing a layer of metal or metal oxide thin film on the substrate; patterning and selectively etching the metal or metal oxide thin film without substantially over etching into the underlying oxide layer; depositing a layer of ferroelectric material; depositing a top electrode on the ferroelectric material; and completing the ferroelectric device.

摘要翻译： 选择性蚀刻用于制造铁电体器件的金属氧化物层的方法包括制备硅衬底，包括在其上形成氧化物层; 在衬底上沉积一层金属或金属氧化物薄膜; 图案化和选择性地蚀刻金属或金属氧化物薄膜，而基本上不会过度蚀刻到下面的氧化物层中; 沉积一层铁电材料; 在铁电材料上沉积顶部电极; 并完成铁电器件。

公开(公告)号：US06951825B2

公开(公告)日：2005-10-04

申请号：US10391294

申请日：2003-03-17

申请人： Tingkai Li ,  Bruce D. Ulrich ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Bruce D. Ulrich ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/3065 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L21/302

CPC分类号： H01L21/32136 ,  H01L21/31116 ,  H01L21/32139 ,  H01L28/65

摘要： A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.

摘要翻译： 蚀刻方法包括准备基板; 沉积第一蚀刻停止层; 形成铱底电极层; 沉积SiN层; 沉积和图案化铝硬掩模; 用SiN选择性蚀刻剂蚀刻未图案化的SiN层，停止在铱底部电极层的水平面上; 用第二选择性蚀刻剂蚀刻第一蚀刻停止层; 将氧化物层沉积并将所述氧化物层CMP沉积到剩余SiN层的水平; 湿式蚀刻SiN层以形成沟槽; 在通过去除SiN层形成的沟槽中沉积一层铁电材料; 沉积一层高K氧化物; 并完成设备，包括金属化。

公开(公告)号：US06819583B2

公开(公告)日：2004-11-16

申请号：US10345726

申请日：2003-01-15

申请人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang

发明人： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang

IPC分类号： G11C1122

CPC分类号： G11C11/22

摘要： A ferroelectric thin film resistor memory array is formed on a substrate and includes plural memory cells arranged in an array of rows and columns; wherein each memory cell includes: a FE resistor having a pair of terminals, and a transistor associated with each resistor, wherein each transistor has a gate, a drain and a source, and wherein the drain of each transistor is electrically connected to one terminal of its associated resistor; a word line connected to the gate of each transistor in a row; a programming line connected to each memory cell in a column; and a bit line connected to each memory cell in a column.

摘要翻译： 铁基薄膜电阻存储阵列形成在基板上，并且包括以行和列为阵列排列的多个存储单元; 其中每个存储器单元包括：具有一对端子的FE电阻器和与每个电阻器相关联的晶体管，其中每个晶体管具有栅极，漏极和源极，并且其中每个晶体管的漏极电连接到 其相关电阻器; 连接到每个晶体管的栅极的字线; 连接到列中的每个存储单元的编程线; 以及连接到列中每个存储单元的位线。

公开(公告)号：US06759250B2

公开(公告)日：2004-07-06

申请号：US10196503

申请日：2002-07-15

申请人： Fengyan Zhang ,  Tingkai Li ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Tingkai Li ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L28/56 ,  H01L21/31604 ,  H01L21/31691 ,  H01L28/75

摘要： The ferroelectric structure including a Pt/Ir layered electrode used in conjunction with a lead germanate (Pb5Ge3O11) thin film is provided. The electrode exhibits good adhesion to the substrate, and barrier properties resistant to oxygen and lead. Ferroelectric properties are improved, without detriment to the leakage current, by using a thin IrO2 layer formed in situ, during the MOCVD lead germanate (Pb5Ge3O11) thin film process. By using a Pt/Ir electrode, a relatively low MOCVD processing temperature is required to achieve c-axis oriented lead germanate (Pb5Ge3O11) thin film. The temperature range of MOCVD c-axis oriented lead germanate (Pb5Ge3O11) thin film on top of Pt/Ir is 400-500° C. Further, a relatively large nucleation density is obtained, as compared to using single-layer iridium electrode. Therefore, the lead germanate (Pb5Ge3O11) thin film has a smooth surface, a homogeneous microstructure, and homogeneous ferroelectric properties. A method of forming the above-mentioned multi-layered electrode ferroelectric structure is also provided.

摘要翻译： 提供了包括与锗酸铅（Pb5Ge3O11）薄膜结合使用的Pt / Ir层叠电极的铁电体结构。 该电极对基材表现出良好的粘合性，并且对氧和铅具有阻挡性能。 在MOCVD锗酸铅（Pb5Ge3O11）薄膜工艺中，通过使用在原位形成的薄的IrO 2层，铁电性能得到改善，而不损害漏电流。 通过使用Pt / Ir电极，需要相对低的MOCVD处理温度来实现c轴取向的锗酸铅（Pb5Ge3O11）薄膜。 Pt / Ir顶部的MOCVD c轴取向锗酸铅（Pb5Ge3O11）薄膜的温度范围为400-500℃。与使用单层铱电极相比，获得了较大的成核密度。 因此，锗酸铅（Pb5Ge3O11）薄膜表面光滑，微观组织均匀，铁电性能均匀。 还提供了形成上述多层电极铁电体结构体的方法。