公开(公告)号：US20170294508A1

公开(公告)日：2017-10-12

申请号：US15144842

申请日：2016-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq ,  Tsung-Mu Yang

IPC: H01L29/06 ,  H01L21/768 ,  H01L23/535 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0653 ,  H01L21/28518 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L23/485 ,  H01L23/535 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a gate structure is formed on the substrate. Next, a recess is formed adjacent to two sides of the gate structure, and an epitaxial layer is formed in the recess, in which a top surface of the epitaxial layer is lower than a top surface of the substrate. Next, a cap layer is formed on the epitaxial layer, in which a top surface of the cap layer is higher than a top surface of the substrate.

公开(公告)号：US09780169B2

公开(公告)日：2017-10-03

申请号：US14876844

申请日：2015-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Yu-Cheng Tung ,  Jyh-Shyang Jenq

IPC: H01L29/08 ,  H01L29/78 ,  H01L27/092

CPC classification number: H01L29/0847 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first conductivity region and a second conductivity region defined thereon, a plurality of first fin structures and at least one first gate structure disposed on the substrate and within the first conductivity region, a plurality of second fin structures and at least one second gate structure disposed on the substrate and within the second conductivity region, at least two first crown epitaxial layers disposed within the first conductivity region, a plurality of second epitaxial layers disposed within the second conductivity region, where the shape of the first crown epitaxial layer is different from that of the second epitaxial layer.

公开(公告)号：US09754938B1

公开(公告)日：2017-09-05

申请号：US15187800

申请日：2016-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Tong-Jyun Huang ,  Shih-Hung Tsai ,  Jia-Rong Wu ,  Tien-Chen Chan ,  Yu-Shu Lin ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.

公开(公告)号：US09685385B1

公开(公告)日：2017-06-20

申请号：US15226929

申请日：2016-08-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/768 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L21/265

CPC classification number: H01L21/823821 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02636 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/66795

Abstract: The present invention provides a method for forming a semiconductor device, including the following steps: first, a substrate is provided, at least one gate is formed on the substrate, a contact etching stop layer (CESL) and a first dielectric layer are formed on the substrate in sequence, afterwards, a first etching process is performed to remove the first dielectric layer, and to expose a top surface and at least one sidewall of the etching stop layer, next, a second etching process is performed to partially remove the contact etching stop layer, and to form at least one epitaxial recess in the substrate. Afterwards, an epitaxial process is performed, to form an epitaxial layer in the epitaxial recess, and a contact structure is then formed on the epitaxial layer.

公开(公告)号：US09553026B1

公开(公告)日：2017-01-24

申请号：US14960447

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Chao-Hung Lin ,  Chien-Ting Lin ,  Li-Chiang Chen ,  Jyh-Shyang Jenq

IPC: H01L21/30 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L21/308 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/3086 ,  H01L27/0886 ,  H01L27/1104 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, and a first mandrel, a second mandrel, a third mandrel, and a fourth mandrel are formed on the substrate. Preferably, the first mandrel and the second mandrel include a first gap therebetween, the second mandrel and the third mandrel include a second gap therebetween, and the third mandrel and the fourth mandrel include a third gap therebetween, in which the first gap is equivalent to the third gap but different from the second gap. Next, spacers are formed adjacent to the first mandrel, the second mandrel, the third mandrel, and the fourth mandrel, and the spacers in the first gap and the third gap are removed.

Abstract translation: 公开了半导体器件的制造方法。 首先，设置基板，在基板上形成第一芯轴，第二心轴，第三心轴，第四心轴。 优选地，第一心轴和第二心轴包括其间的第一间隙，第二心轴和第三心轴在其间包括第二间隙，并且第三心轴和第四心轴在其间包括第三间隙，其中第一间隙等于 第三个差距，但与第二个差距不同。 接下来，在第一心轴，第二心轴，第三心轴和第四心轴附近形成间隔物，并且去除第一间隙和第三间隙中的间隔物。

公开(公告)号：US20160380081A1

公开(公告)日：2016-12-29

申请号：US14818322

申请日：2015-08-05

Applicant: United Microelectronics Corp.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L29/66795 ,  H01L21/76224 ,  H01L29/7851

Abstract: A FinFET includes a substrate. Numerous fin structures are defined on the substrate. A gate structure crosses each fin structure. Two epitaxial layers are disposed at two side of the gate structure, respectively. Each epitaxial layer has a top surface including a second recessed and protruding profile. A contact plug contacts the second recessed and protruding profile. The second recessed and protruding profile increases the contact area between the contact plug and the epitaxial layer.

Abstract translation: FinFET包括衬底。 在衬底上限定了许多翅片结构。 栅极结构跨越每个鳍结构。 两个外延层分别设置在栅极结构的两侧。 每个外延层具有包括第二凹入和突出轮廓的顶表面。 接触插头接触第二凹入和突出的轮廓。 第二凹入和突出的轮廓增加了接触插塞和外延层之间的接触面积。

公开(公告)号：US20160365344A1

公开(公告)日：2016-12-15

申请号：US14792591

申请日：2015-07-06

Applicant: United Microelectronics Corp.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.

Abstract translation: 本发明提供了一种半导体结构，其包括具有第一鳍结构和设置在其上的第二鳍结构的衬底，位于第一鳍结构和第二鳍结构之间的第一隔离区，与第一鳍结构相对的第二隔离区 并且至少设置在第一鳍片结构和第二鳍片结构侧的外延层。 外延层具有从第一鳍结构延伸到第二鳍结构的底表面，底表面低于第一隔离区的底表面和第二隔离区的顶表面。

公开(公告)号：US20160358827A1

公开(公告)日：2016-12-08

申请号：US15241077

申请日：2016-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Wei-Chi Cheng ,  Jyh-Shyang Jenq

IPC: H01L21/84 ,  H01L21/306 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H01L21/762 ,  H01L21/308

CPC classification number: H01L21/845 ,  H01L21/02238 ,  H01L21/02365 ,  H01L21/02367 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/7624 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-shaped structure includes the following step. A substrate having a first area and a second area is provided. An epitaxial structure is formed in the first area. An epitaxial structure is formed in the second area after the epitaxial structure in the first area is formed, wherein the surface area of the epitaxial structure in the first area is different from the surface area of the epitaxial structure in the second area.

Abstract translation: 形成翅片状结构的方法包括以下步骤。 提供具有第一区域和第二区域的衬底。 在第一区域中形成外延结构。 在形成第一区域中的外延结构之后，在第二区域中形成外延结构，其中第一区域中的外延结构的表面积与第二区域中的外延结构的表面积不同。

公开(公告)号：US09502410B1

公开(公告)日：2016-11-22

申请号：US14792591

申请日：2015-07-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Li-Wei Feng ,  Shih-Hung Tsai ,  Hon-Huei Liu ,  Chao-Hung Lin ,  Nan-Yuan Huang ,  Jyh-Shyang Jenq

IPC: H01L27/088 ,  H01L29/78 ,  H01L21/28 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L27/092

CPC classification number: H01L21/823431 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/42372 ,  H01L29/7842 ,  H01L29/785

Abstract: The present invention provides a semiconductor structure, including a substrate having a first fin structure and a second fin structure disposed thereon, a first isolation region located between the first fin structure and the second fin structure, a second isolation region located opposite the first fin structure from the first isolation region, and at least an epitaxial layer disposed on the side of the first fin structure and the second fin structure. The epitaxial layer has a bottom surface, the bottom surface extending from the first fin structure to the second fin structure, and the bottom surface is lower than a bottom surface of the first isolation region and a top surface of the second isolation region.

Abstract translation: 本发明提供了一种半导体结构，其包括具有第一鳍结构和设置在其上的第二鳍结构的衬底，位于第一鳍结构和第二鳍结构之间的第一隔离区，与第一鳍结构相对的第二隔离区 并且至少设置在第一鳍片结构和第二鳍片结构侧的外延层。 外延层具有从第一鳍结构延伸到第二鳍结构的底表面，底表面低于第一隔离区的底表面和第二隔离区的顶表面。

公开(公告)号：US09443954B2

公开(公告)日：2016-09-13

申请号：US15009808

申请日：2016-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Yu-Hsiang Hung ,  Ssu-I Fu ,  Jyh-Shyang Jenq

IPC: H01L27/02 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/28

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966

Abstract: The present invention provides a method for forming a semiconductor device having a metal gate. The method includes firstly, a substrate is provided, and a first semiconductor device and a second semiconductor device are formed on the substrate, having a first gate trench and a second trench respectively. Next, a bottom barrier layer is formed in the first gate trench and a second trench. Afterwards, a first pull back step is performed, to remove parts of the bottom barrier layer, and a first work function metal layer is then formed in the first gate trench. Next, a second pull back step is performed, to remove parts of the first work function metal layer, wherein the topmost portion of the first work function metal layer is lower than the openings of the first gate trench and the second gate trench.

Abstract translation: 本发明提供一种形成具有金属栅极的半导体器件的方法。 该方法首先包括衬底，并且在衬底上形成第一半导体器件和第二半导体器件，分别具有第一栅极沟槽和第二沟槽。 接下来，在第一栅极沟槽和第二沟槽中形成底部阻挡层。 之后，执行第一回拉步骤以去除底部阻挡层的部分，然后在第一栅极沟槽中形成第一功函数金属层。 接下来，执行第二拉回步骤以去除第一功函数金属层的部分，其中第一功函数金属层的最顶部比第一栅沟槽和第二栅沟的开口低。