公开(公告)号：US09917038B1

公开(公告)日：2018-03-13

申请号：US15347599

申请日：2016-11-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/4828 ,  H01L21/481 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49527 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49558 ,  H01L23/49582 ,  H01L23/49586 ,  H01L23/49805 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/45565 ,  H01L2224/45572 ,  H01L2224/48091 ,  H01L2224/48235 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2224/45664 ,  H01L2224/45644

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US20160064310A1

公开(公告)日：2016-03-03

申请号：US14794715

申请日：2015-07-08

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Saravuth Sirinorakul ,  Antonio Bambalan Dimaano, Jr. ,  Rui Huang

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/66 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4832 ,  H01L21/565 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48249 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/85399

Abstract: A method of and device for making a semiconductor package. The method comprises etching a first side of a metallic piece forming a leadframe with one or more wire bonding pads, applying a first protective layer on the first side, etching a second side of the metallic piece forming one or more conductive terminals, and applying a second protective layer on the second side. The semiconductor package comprises wire bonding pads in pillars structure surrounding a die attached to the leadframe. One or more terminals are on the bottom side of the semiconductor package.

Abstract translation: 一种用于制造半导体封装的方法和装置。 该方法包括使用一个或多个引线接合焊盘蚀刻形成引线框架的金属片的第一侧，在第一侧上施加第一保护层，蚀刻形成一个或多个导电端子的金属片的第二侧， 第二侧的第二保护层。 半导体封装包括围绕附接到引线框架的管芯的柱状结构的引线接合焊盘。 一个或多个端子位于半导体封装的底侧。

公开(公告)号：US20220270942A1

公开(公告)日：2022-08-25

申请号：US17680308

申请日：2022-02-25

Applicant: UTAC Headquarters Pte. Ltd.

Inventor： Nataporn Charusabha ,  Kunakorn Kaoson ,  Saravuth Sirinorakul ,  Sukhontip Jaikongkaew ,  Il Kwon Shim

IPC: H01L23/24 ,  H01L23/00 ,  H01L23/367 ,  H01L21/56

Abstract: A flip chip package is disclosed. The package includes a leadframe surrounding a flip chip. The leadframe and flip chip are encapsulated by a mold compound. The leadframe provides package support to enhance the mechanical stability of the package. In some cases, a heat dissipating structure is disposed on top of the package, connecting the flip chip to enhance heat dissipation.

公开(公告)号：US10734247B2

公开(公告)日：2020-08-04

申请号：US15803605

申请日：2017-11-03

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US10600741B1

公开(公告)日：2020-03-24

申请号：US15832638

申请日：2017-12-05

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Suebphong Yenrudee ,  Chanapat Kongpoung ,  Sant Hongsongkiat ,  Siriwanna Ounkaew ,  Chatchawan Injan ,  Saravuth Sirinorakul

IPC: H01L23/552 ,  H01L25/065 ,  H01L23/495 ,  H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L21/3205 ,  H01L21/3105 ,  H01L21/78 ,  H01L23/31

Abstract: Methods of manufacturing semiconductor packages with metal-plated shields include roughening surfaces of a molding compound by an abrasion process such that the surfaces have an unnatural surface roughness that is rougher than a natural surface roughness. In one embodiment, the method includes obtaining a molded array including a plurality of dies coupled to a substrate and a molding compound encapsulating the plurality of dies, coating all exposed surfaces of the molding compound with an adhesion promoter material, heating the molded array with an adhesion promoter material such that the adhesion promoter material reacts with a portion of the molding compound, resulting in a baked film, and etching away the baked film, resulting in the molding compound having the roughened surfaces. Preferably, the method also includes depositing a catalyst material on the roughened surfaces before a metal layer is coated on the roughened surfaces to speed up the time for the metal layer to adhere to the roughened surfaces.

公开(公告)号：US10515878B1

公开(公告)日：2019-12-24

申请号：US15601963

申请日：2017-05-22

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Somchai Nondhasitthichai ,  Saravuth Sirinorakul ,  Woraya Benjasukul

IPC: H01L23/495 ,  H01L21/78 ,  H01L23/31

Abstract: Embodiments of the present invention are directed to a semiconductor package with partial plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface, a second surface that is flush with one of the side surfaces, and a third surface between the first surface and the second surface. Each of the side surfaces can include a step such that the area of the bottom surface is differently sized from the area of the top surface and the third surface is located at the step. The first surface is plated, while the second surface is exposed (not plated). At least a portion of the third surface is plated.

公开(公告)号：US10361146B2

公开(公告)日：2019-07-23

申请号：US16243972

申请日：2019-01-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Keith M. Edwards ,  Suebphong Yenrudee ,  Albert Loh

IPC: H01L21/00 ,  H01L23/495 ,  H01L23/31 ,  H01L21/78 ,  H01L21/48

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple leadframe routing layers in a plated and etched copper terminal semiconductor package by removing unwanted areas of each leadframe to create conductive paths on an associated leadframe layer of the semiconductor package.

公开(公告)号：US10325782B2

公开(公告)日：2019-06-18

申请号：US15673212

申请日：2017-08-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.

公开(公告)号：US10242934B1

公开(公告)日：2019-03-26

申请号：US15649466

申请日：2017-07-13

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul

IPC: H01L23/31 ,  H01L23/495

Abstract: Embodiments of the present invention are directed to a semiconductor package with full plating on contact side surfaces. The semiconductor package includes a top surface, a bottom surface opposite the top surface, and side surfaces between the top and bottom surfaces. Contacts are located on peripheral edges of the bottom surface. Each of the contacts includes a first surface that is flush with the bottom surface and a second surface that is at one of the side surfaces. The first surface and the second surface of each of the contacts are continuously plated. Portions of an internal plating layer are exposed along the side surfaces of the semiconductor package. The semiconductor package has a molding compound at least partially encapsulating the contacts, wherein the surface of a first part of the molding compound and the surface of a second part of the molding compound have different surface texture.

公开(公告)号：US10032645B1

公开(公告)日：2018-07-24

申请号：US15347695

申请日：2016-11-09

Applicant: UTAC Headquarters PTE. LTD.

Inventor： Saravuth Sirinorakul ,  Suebphong Yenrudee

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/495 ,  H01L21/56

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is fondled from multiple molding routing layers in a leadframe land grid array semiconductor package by using a laser to blast away un-designed conductive areas to create conductive paths on each molding compound layer of the semiconductor package.