公开(公告)号：US20190122920A1

公开(公告)日：2019-04-25

申请号：US16226498

申请日：2018-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Hsuan-Tai Hsu ,  Kuan-Hsuan Ku

IPC: H01L21/768 ,  H01L29/417 ,  H01L23/522 ,  H01L21/311

Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.

公开(公告)号：US20180033874A1

公开(公告)日：2018-02-01

申请号：US15660919

申请日：2017-07-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Shui-Yen Lu

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02667 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.

公开(公告)号：US12040392B2

公开(公告)日：2024-07-16

申请号：US18075427

申请日：2022-12-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Ming-Hua Chang ,  Shui-Yen Lu

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/7786 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7787

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.

公开(公告)号：US20220367693A1

公开(公告)日：2022-11-17

申请号：US17396793

申请日：2021-08-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Hua Chang ,  Po-Wen Su ,  Chih-Tung Yeh

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L21/311

Abstract: A semiconductor structure includes a substrate, a stacked structure on the substrate, an insulating layer on the stacked structure, a passivation layer on the insulating layer, and a contact structure through the passivation layer and the insulating layer and directly contacting the stacked structure. The insulating layer has an extending portion protruding from a sidewall of the passivation layer and adjacent to a surface of the stacked structure directly contacting the contact structure.

公开(公告)号：US20210249529A1

公开(公告)日：2021-08-12

申请号：US16809524

申请日：2020-03-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Ming-Hua Chang ,  Shui-Yen Lu

IPC: H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/66 ,  H01L29/06

Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.

公开(公告)号：US10483158B2

公开(公告)日：2019-11-19

申请号：US16226498

申请日：2018-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Hsuan-Tai Hsu ,  Kuan-Hsuan Ku

IPC: H01L21/768 ,  H01L29/417 ,  H01L23/522 ,  H01L21/311 ,  H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.

公开(公告)号：US20180151685A1

公开(公告)日：2018-05-31

申请号：US15863990

申请日：2018-01-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Zhen Wu ,  Hsiao-Pang Chou ,  Chiu-Hsien Yeh ,  Shui-Yen Lu ,  Jian-Wei Chen

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40

CPC classification number: H01L29/512 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.

公开(公告)号：US20170294523A1

公开(公告)日：2017-10-12

申请号：US15095154

申请日：2016-04-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhen Wu ,  Chiu-Hsien Yeh ,  Po-Wen Su ,  Kuan-Ying Lai

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/304 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/66795 ,  H01L21/02603 ,  H01L21/28158 ,  H01L21/304 ,  H01L21/76897 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first organic layer on the substrate; patterning the first organic layer to form an opening; forming a second organic layer in the opening; and removing the first organic layer to form a patterned second organic layer on the substrate.

公开(公告)号：US09443741B1

公开(公告)日：2016-09-13

申请号：US14748257

申请日：2015-06-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wen Su ,  Zhi-Jian Wang ,  Cheng-Chang Wu ,  Hsin-Yu Hsieh ,  Shui-Yen Lu

IPC: H01L21/302 ,  H01L21/461 ,  H01L21/308

CPC classification number: H01L21/0271 ,  H01L21/31055 ,  H01L21/31058

Abstract: An etching method includes forming a high density structure and a low density structure on a substrate. A first material layer is formed to cover both structures. Part of the low density structure is exposed through the first material layer. A second material layer is formed to cover the first material layer. The second material layer is etched to remove the second material layer on the high density structure and part of the second material layer on the low density structure. The first material layer on the high density structure and the second material layer on the low density structure are simultaneously etched. The first material layer is etched to expose a first portion of the high density structure and a second portion of the low density structure. Finally, the first portion and the second portion are removed.

Abstract translation: 蚀刻方法包括在基板上形成高密度结构和低密度结构。 形成第一材料层以覆盖两个结构。 低密度结构的一部分通过第一材料层暴露。 形成第二材料层以覆盖第一材料层。 蚀刻第二材料层以去除高密度结构上的第二材料层和低密度结构上的第二材料层的一部分。 同时蚀刻高密度结构上的第一材料层和低密度结构上的第二材料层。 蚀刻第一材料层以暴露高密度结构的第一部分和低密度结构的第二部分。 最后，去除第一部分和第二部分。

公开(公告)号：US09117904B2

公开(公告)日：2015-08-25

申请号：US14608165

申请日：2015-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shyan-Liang Chou ,  Tsung-Min Kuo ,  Po-Wen Su ,  Chun-Mao Chiou ,  Feng-Mou Chen

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/4983 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7843

Abstract: A semiconductor structure includes a substrate, a gate electrode disposed on the substrate, wherein the gate electrode has a first top surface. Agate dielectric layer is disposed between the substrate and the gate electrode. A silicon carbon nitride spacer surrounds the gate electrode, wherein the silicon carbon nitride spacer has a second top surface not higher than the first top surface. A silicon oxide spacer surrounds the silicon carbon nitride spacer.

Abstract translation: 半导体结构包括衬底，设置在衬底上的栅电极，其中栅电极具有第一顶表面。 玛瑙电介质层设置在基板和栅电极之间。 硅碳氮化物间隔物环绕栅电极，其中硅氮化物间隔物具有不高于第一顶表面的第二顶表面。 硅氧化物间隔物包围硅氮化硅间隔物。