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    Magnetoresistive random access memory device and method for fabricating the same
    21.
    发明授权
    Magnetoresistive random access memory device and method for fabricating the same 有权

    公开(公告)号：US11258005B2

    公开(公告)日：2022-02-22

    申请号：US16656304

    申请日：2019-10-17

    Applicant: United Microelectronics Corp.

    Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ting-An Chien

    IPC: H01L43/12 ,  H01L43/02 ,  H01L43/10

    Abstract: A cell structure of magnetoresistive RAM includes a synthetic anti-ferromagnetic (SAF) layer to serve as a pinned layer; a barrier layer, disposed on the SAF layer; and a magnetic free layer, disposed on the barrier layer. The SAF layer includes: a first magnetic layer; a second magnetic layer; and a spacer layer of a first metal element sandwiched between the first magnetic layer and the second magnetic layer. The first metal element is phase separated from a second metal element of the first magnetic layer and the second magnetic layer interfacing with the spacer layer.

    Memory cell and forming method thereof
    23.
    发明授权
    Memory cell and forming method thereof 有权

    公开(公告)号：US11101324B2

    公开(公告)日：2021-08-24

    申请号：US16513719

    申请日：2019-07-17

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Chin-Chia Yang ,  Ting-An Chien

    IPC: H01L27/24 ,  H01L27/28 ,  H01L45/00 ,  H01L51/00 ,  H01L51/05 ,  H01L51/10

    Abstract: A memory cell includes a first conductive line, a lower electrode, a carbon nano-tube (CNT) layer, a middle electrode, a resistive layer, a top electrode and a second conductive line. The first conductive line is disposed over a substrate. The lower electrode is disposed over the first conductive line. The carbon nano-tube (CNT) layer is disposed over the lower electrode. The middle electrode is disposed over the carbon nano-tube layer, thereby the lower electrode, the carbon nano-tube (CNT) layer and the middle electrode constituting a nanotube memory part. The resistive layer is disposed over the middle electrode. The top electrode is disposed over the resistive layer, thereby the middle electrode, the resistive layer and the top electrode constituting a resistive memory part. The second conductive line is disposed over the top electrode.

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    26.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 审中-公开
    半导体结构及其工艺

    公开(公告)号：US20160365315A1

    公开(公告)日：2016-12-15

    申请号：US14738943

    申请日：2015-06-15

    Applicant: United Microelectronics Corp.

    Inventor： Wei-Hsin Liu ,  Bin-Siang Tsai

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

    CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/32 ,  H01L21/76825 ,  H01L21/76834 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

    Abstract: A semiconductor process includes the following steps. Metal patterns are formed on a first dielectric layer. A modifiable layer is formed to cover the metal patterns and the first dielectric layer. A modification process is performed to modify a part of the modifiable layer on top sides of the metal patterns, thereby top masks being formed. A removing process is performed to remove a part of the modifiable layer on sidewalls of the metal patterns but preserve the top masks. A dielectric layer having voids under the top masks and between the metal patterns is formed. Moreover, the present invention also provides a semiconductor structure formed by said semiconductor process.

    Abstract translation: 半导体工艺包括以下步骤。 金属图案形成在第一电介质层上。 形成可修饰层以覆盖金属图案和第一介电层。 执行修改处理以修改金属图案的顶侧上的可修改层的一部分，从而形成顶部掩模。 执行去除过程以去除金属图案的侧壁上的可修饰层的一部分，但保留顶部掩模。 形成在顶部掩模之下和金属图案之间具有空隙的电介质层。 此外，本发明还提供了由所述半导体工艺形成的半导体结构。

    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
    28.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 有权

    公开(公告)号：US20250079293A1

    公开(公告)日：2025-03-06

    申请号：US18379670

    申请日：2023-10-13

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tai-Cheng Hou ,  Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai

    IPC: H01L23/522 ,  H01L21/768

    Abstract: A semiconductor device and a method of fabricating the same, includes at least one dielectric layer, a conductive structure, and a first insulator. The at least one dielectric layer includes a stacked structure having a low-k dielectric layer, an etching stop layer, and a conductive layer between the low-k dielectric layer and the etching stop layer. The conductive structure is disposed in the first dielectric layer. The first insulator is disposed between the conductive layer and the conductive structure.

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