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    Semiconductor device
    22.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11476348B2

    公开(公告)日：2022-10-18

    申请号：US17151683

    申请日：2021-01-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chuan-Chang Wu ,  Zhen Wu ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

    IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/306 ,  H01L21/764 ,  H01L29/786

    Abstract: A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.

    Method of performing etching process
    23.
    发明授权
    Method of performing etching process 有权
    执行蚀刻工艺的方法

    公开(公告)号：US09385000B2

    公开(公告)日：2016-07-05

    申请号：US14162755

    申请日：2014-01-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen

    IPC: H01L21/00 ,  H01L21/311 ,  H01L21/027 ,  H01L21/768

    CPC classification number: H01L21/31144 ,  H01L21/0276 ,  H01L21/31133 ,  H01L21/76816

    Abstract: A method of performing an etching process is provided. A substrate is provided, wherein a first region and a second region are defined on the substrate, and an overlapping region of the first region and the second region is defined as a third region. A tri-layer structure comprising an organic layer, a bottom anti-reflection coating (BARC), and a photoresist layer is formed on the substrate. The photoresist layer and the BARC in the second region are removed. An etching process is performed to remove the organic layer in the second region by using the BARC and/or the photoresist layer as a mask, wherein the etching process uses an etchant comprises CO2.

    Abstract translation: 提供了一种执行蚀刻工艺的方法。 提供了一种衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。 在基板上形成包括有机层，底部防反射涂层（BARC）和光致抗蚀剂层的三层结构。 去除第二区域中的光致抗蚀剂层和BARC。 通过使用BARC和/或光致抗蚀剂层作为掩模，进行蚀刻工艺以去除第二区域中的有机层，其中蚀刻工艺使用蚀刻剂包括CO 2。

    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME
    24.
    发明申请
    SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD FOR THE SAME 有权
    半导体结构及其制造方法

    公开(公告)号：US20150279957A1

    公开(公告)日：2015-10-01

    申请号：US14230223

    申请日：2014-03-31

    Applicant: United Microelectronics Corp.

    Inventor： Yu-Ping Wang ,  Jyh-Shyang Jenq ,  Yu-Hsiang Lin ,  Hsuan-Hsu Chen ,  Chien-Hao Chen ,  Yi-Han Ye

    IPC: H01L29/66 ,  H01L29/78

    CPC classification number: H01L29/785 ,  H01L29/66795

    Abstract: A semiconductor structure and a manufacturing method for the same are disclosed. The semiconductor structure includes a first gate structure, a second gate structure and a second dielectric spacer. Each of the first gate structure and the second gate structure adjacent to each other includes a first dielectric spacer. The second dielectric spacer is on one of opposing sidewalls of the first gate structure and without being disposed on the dielectric spacer of the second gate structure.

    Abstract translation: 公开了一种半导体结构及其制造方法。 半导体结构包括第一栅极结构，第二栅极结构和第二电介质间隔物。 彼此相邻的第一栅极结构和第二栅极结构中的每一个包括第一电介质间隔物。 第二电介质间隔物位于第一栅极结构的相对侧壁中的一个上，而不设置在第二栅极结构的电介质间隔物上。

    Manufacturing Method of Non-Planar FET
    25.
    发明申请
    Manufacturing Method of Non-Planar FET 有权
    非平面FET的制造方法

    公开(公告)号：US20150004766A1

    公开(公告)日：2015-01-01

    申请号：US14487103

    申请日：2014-09-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen ,  Ying-Chih Lin ,  Chien-Ting Lin ,  Hsuan-Hsu Chen

    IPC: H01L29/66 ,  H01L29/51

    CPC classification number: H01L29/66795 ,  H01L29/51 ,  H01L29/66818 ,  H01L29/785

    Abstract: The present invention provides a non-planar FET which includes a substrate, a fin structure, a sub spacer, a gate, a dielectric layer and a source/drain region. The fin structure is disposed on the substrate. The sub spacer is disposed only on a middle sidewall of the fin structure. The gate is disposed on the fin structure. The dielectric layer is disposed between the fin structure and the gate. The source/drain region is disposed in the fin structure. The present invention further provides a method of forming the same.

    Abstract translation: 本发明提供一种非平面FET，其包括基板，鳍结构，子间隔物，栅极，电介质层和源极/漏极区域。 翅片结构设置在基板上。 子间隔件仅设置在翅片结构的中间侧壁上。 门设置在翅片结构上。 介电层设置在翅片结构和栅极之间。 源/漏区设置在鳍结构中。 本发明还提供一种形成该方法的方法。

    Patterning method
    26.
    发明授权
    Patterning method 有权
    图案化方法

    公开(公告)号：US08916475B1

    公开(公告)日：2014-12-23

    申请号：US14070262

    申请日：2013-11-01

    Applicant: United Microelectronics Corp.

    Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen ,  Cheng-Hsing Chuang

    IPC: H01L21/311 ,  H01L21/308

    CPC classification number: H01L21/3085 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/823431

    Abstract: A patterning method is provided. A mask composite layer and a first tri-layer photoresist are sequentially formed on a target layer. A first etching is performed to the mask composite layer, using the first tri-layer photoresist as a mask, to form at least one first opening in an upper portion of the mask composite layer. The first tri-layer photoresist is removed. A second tri-layer photoresist is formed on the mask composite layer. A second etching is performed to the mask composite layer, using the second tri-layer photoresist as a mask, to form at least one second opening in the upper portion of the mask composite layer. The second tri-layer photoresist is removed. A lower portion of the mask composite layer is patterned by using the upper portion of the mask composite layer as a mask. The target layer is patterned by using the patterned mask composite layer as a mask.

    Abstract translation: 提供了图案化方法。 在目标层上依次形成掩模复合层和第一三层光致抗蚀剂。 使用第一三层光致抗蚀剂作为掩模对掩模复合层进行第一蚀刻，以在掩模复合层的上部中形成至少一个第一开口。 去除第一三层光致抗蚀剂。 在掩模复合层上形成第二三层光致抗蚀剂。 使用第二三层光致抗蚀剂作为掩模对掩模复合层进行第二蚀刻，以在掩模复合层的上部形成至少一个第二开口。 去除第二三层光致抗蚀剂。 通过使用掩模复合层的上部作为掩模来对掩模复合层的下部进行图案化。 通过使用图案化掩模复合层作为掩模来对目标层进行图案化。

    Manufacturing method of semiconductor structure
    27.
    发明授权
    Manufacturing method of semiconductor structure 有权
    半导体结构的制造方法

    公开(公告)号：US08883648B1

    公开(公告)日：2014-11-11

    申请号：US14020948

    申请日：2013-09-09

    Applicant: United Microelectronics Corp.

    Inventor： Ming-Da Hsieh ,  Yu-Tsung Lai ,  Hsuan-Hsu Chen

    IPC: H01L21/311 ,  H01L21/033 ,  H01L21/768 ,  H01L21/00

    CPC classification number: H01L21/76802 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76879

    Abstract: A manufacturing method of a semiconductor structure is disclosed. The manufacturing method includes the following steps: providing an underlying layer; forming a tri-layered photoresist on the underlying layer, which comprises forming a bottom photoresist layer on the underlying layer, forming a silicon-containing material layer on the bottom photoresist layer, and forming a patterned photoresist layer on the silicon-containing material layer; performing an atomic layer deposition (ALD) process for forming a thin layer on the tri-layered photoresist; and performing an etching process for forming a via hole, which comprises etching the silicon-containing material layer according to the thin layer on the tri-layered photoresist.

    Abstract translation: 公开了一种半导体结构的制造方法。 该制造方法包括以下步骤：提供下层; 在下层上形成三层光致抗蚀剂，其包括在下层形成底部光致抗蚀剂层，在底部光致抗蚀剂层上形成含硅材料层，并在含硅材料层上形成图案化的光致抗蚀剂层; 执行在三层光致抗蚀剂上形成薄层的原子层沉积（ALD）工艺; 以及进行用于形成通孔的蚀刻工艺，其包括在三层光致抗蚀剂上根据薄层蚀刻含硅材料层。

    Semiconductor device and manufacturing method thereof
    28.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US10937893B2

    公开(公告)日：2021-03-02

    申请号：US16544830

    申请日：2019-08-19

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chuan-Chang Wu ,  Zhen Wu ,  Hsuan-Hsu Chen ,  Chun-Lung Chen

    IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/764 ,  H01L29/786

    Abstract: A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.

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