公开(公告)号：US12132011B2

公开(公告)日：2024-10-29

申请号：US17408505

申请日：2021-08-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Chu-Chun Chang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/522

CPC classification number: H01L23/564 ,  H01L23/3192 ,  H01L23/5226 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2924/3512

Abstract: An integrated circuit device includes a substrate; an integrated circuit region on the substrate, said integrated circuit region comprising a dielectric stack; a seal ring disposed in said dielectric stack and around a periphery of the integrated circuit region; a trench around the seal ring and exposing a sidewall of the dielectric stack; and a moisture blocking layer continuously covering the integrated circuit region and extending to the sidewall of the dielectric stack, thereby sealing a boundary between two adjacent dielectric films in the dielectric stack.

公开(公告)号：US20240332201A1

公开(公告)日：2024-10-03

申请号：US18743110

申请日：2024-06-14

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L23/538 ,  H01L27/06 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L27/0623 ,  H01L29/66242 ,  H01L29/737

Abstract: A semiconductor structure includes following components. A first substrate has a first surface and a second surface opposite to each other. An HBT device is located on the first substrate and includes a collector, a base, and an emitter. A first interconnect structure is electrically connected to the base, located on the first surface, and extends to the second surface. A second interconnect structure is electrically connected to the emitter, located on the first surface, and extends to the second surface. A third interconnect structure is located on the second surface and electrically connected to the collector. An MOS transistor device is located on a second substrate and includes a gate, a first source and drain region, and a second source and drain region. Interconnect structures on the second substrate electrically connect the base to the first source and drain region and electrically connect the emitter to the gate.

公开(公告)号：US20240178137A1

公开(公告)日：2024-05-30

申请号：US18108024

申请日：2023-02-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： XINGXING CHEN ,  Ching-Yang Wen ,  Purakh Raj Verma

IPC: H01L23/528 ,  H01L23/522 ,  H01Q1/38

CPC classification number: H01L23/528 ,  H01L23/5227 ,  H01Q1/38

Abstract: A method for determining antenna rule for a radio-frequency (RF) device includes the steps of forming a gate structure on a substrate, forming a source/drain region adjacent to the gate structure, forming a first metal routing on the source/drain region, and then forming a second metal routing on the gate structure. Preferably, a sum of an area of the first metal routing and an area of the second metal routing divided by an area of the gate structure is less than a ratio.

公开(公告)号：US11955292B2

公开(公告)日：2024-04-09

申请号：US17987766

申请日：2022-11-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Ching-Yang Wen ,  Xingxing Chen ,  Chao Jin

IPC: H01G4/38 ,  H01G4/008 ,  H01L21/288 ,  H01L21/321 ,  H01L23/522 ,  H01L23/528 ,  H01L27/01 ,  H01L49/02

CPC classification number: H01G4/385 ,  H01G4/008 ,  H01L21/2885 ,  H01L21/3212 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/01 ,  H01L28/75 ,  H01L28/91

Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.

公开(公告)号：US20240047266A1

公开(公告)日：2024-02-08

申请号：US17880685

申请日：2022-08-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Liang Liao ,  Chee Hau Ng ,  Ching-Yang Wen ,  Purakh Raj Verma

IPC: H01L21/762 ,  H01L21/304 ,  H01L21/768

CPC classification number: H01L21/76251 ,  H01L21/304 ,  H01L21/76865

Abstract: A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.

公开(公告)号：US11652017B2

公开(公告)日：2023-05-16

申请号：US17080855

申请日：2020-10-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Kuo-Yuh Yang ,  Chia-Huei Lin

IPC: H01L23/36 ,  H01L21/48 ,  H01L23/367

CPC classification number: H01L23/367 ,  H01L21/4803

Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.

公开(公告)号：US20220328700A1

公开(公告)日：2022-10-13

申请号：US17849718

申请日：2022-06-27

Applicant: United Microelectronics Corp.

Inventor： Purakh Raj Verma ,  Su Xing

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66

Abstract: A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

公开(公告)号：US20220068766A1

公开(公告)日：2022-03-03

申请号：US17521805

申请日：2021-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Pin Hsu ,  Chih-Jung Wang ,  Chu-Chun Chang ,  Kuo-Yuh Yang ,  Chia-Huei Lin ,  Purakh Raj Verma

IPC: H01L23/482 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/485

Abstract: A semiconductor structure with an air gap includes a dielectric stack having a first dielectric layer on a substrate, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer. A first conductive layer and a second conductive layer are disposed in the dielectric stack. The first conductive layer and the second conductive layer are coplanar. A cross-like-shaped air gap is disposed in the dielectric stack between the first and second conductive layers. An oxide layer is disposed on a sidewall of the second dielectric layer within the cross-like-shaped air gap.

公开(公告)号：US20220059459A1

公开(公告)日：2022-02-24

申请号：US17520725

申请日：2021-11-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L23/528 ,  H01L29/08 ,  H01L29/78 ,  H01L27/12 ,  H01L29/423

Abstract: A semiconductor device includes a first gate line and a second gate line extending along a first direction, a third gate line extending along a second direction and between and directly contacting the first gate line and the second gate line, a drain region adjacent to one side of the third gate line, a fourth gate line extending along the second direction and between and directly contacting the first gate line and the second gate line, and a first metal interconnection extending along the second direction between the third gate line and the fourth gate line. Preferably, the third gate line includes a first protrusion and the fourth gate line includes a second protrusion.

公开(公告)号：US20210351066A1

公开(公告)日：2021-11-11

申请号：US17380057

申请日：2021-07-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Purakh Raj Verma ,  Chia-Huei Lin ,  Kuo-Yuh Yang

IPC: H01L21/762 ,  H01L21/761 ,  H01L21/311 ,  H01L21/763 ,  H01L21/764 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first trench and a second trench in a substrate as a depth of the first trench is greater than a depth of the second trench; forming a liner in the first trench and the second trench; forming a first patterned mask on the substrate to cover the second trench; removing the liner in the first trench; removing the first patterned mask; and forming an insulating layer in the first trench and the second trench to form a trap rich isolation structure in the first trench and a deep trench isolation structure in the second trench.