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21.发明申请MANUFACTURING METHOD AND INTEGRATED CIRCUIT HAVING A LIGHT PATH TO A PIXILATED ELEMENT 有权制造方法和集成电路有一个光线路到一个被粉碎的元素公开(公告)号：US20110012158A1
公开(公告)日：2011-01-20
申请号：US12922072
申请日：2009-03-09
IPC分类号： H01L33/58 , H01L31/18 , H01L31/0232 , H01L33/00
CPC分类号： H01L27/14625 , H01L27/14621 , H01L27/14636 , H01L27/14685
摘要： The present invention relates to a manufacturing method of an integrated circuit (IC) comprising a substrate (10) comprising a pixelated element (12) and a light path (38) to the pixelated element (12). The IC comprises a first dielectric layer (14) covering the substrate (10) but not the pixilated element (12), a first metal layer (16) covering a part of the first dielectric layer (14), a second dielectric layer (18) covering a further part of first dielectric layer (14), a second metal layer (20) covering a part of the second dielectric layer (18) and extending over the pixelated element (12) and a part of the first metal layer (16), the first metal layer (16) and the second metal layer (20) forming an air-filled light path (38) to the pixelated element (12). The air-filled light path (38) is formed by creation of holes in the first dielectric layer (14) and the second dielectric layer (18), filling the holes with sacrificial materials, and removal of the sacrificial materials after deposition and patterning of the second metal layer (20). This yields an IC having a low-loss light path to the pixelated element (12). The light path may act as a color filter, e.g. a Fabry-Perot color filter.
摘要翻译： 本发明涉及一种集成电路（IC）的制造方法，该集成电路（IC）包括基板（10），该基板（10）包括像素化元件（12）和到像素化元件（12）的光路（38）。 所述IC包括覆盖所述衬底（10）而不是所述像素化元件（12）的第一介电层（14），覆盖所述第一介电层（14）的一部分的第一金属层（16），第二介电层（18） ）覆盖第一介电层（14）的另一部分，覆盖第二介电层（18）的一部分并在像素化元件（12）上延伸的第二金属层（20）和第一金属层（16）的一部分 ），第一金属层（16）和第二金属层（20）形成到像素化元件（12）的充气光路（38）。 充气光路（38）通过在第一电介质层（14）和第二电介质层（18）中产生孔而形成，用牺牲材料填充孔，并且在沉积和图案化之后去除牺牲材料 第二金属层（20）。 这产生具有到像素化元件（12）的低损耗光路的IC。 光路可以用作滤色器，例如， 法布里 - 珀罗滤镜。
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公开(公告)号：US08174041B2
公开(公告)日：2012-05-08
申请号：US12864752
申请日：2009-01-27
CPC分类号： H01L25/167 , H01L31/105 , H01L31/153 , H01L33/486 , H01L2224/16225 , H01L2924/0002 , H05B33/0803 , H05B33/0866 , H01L2924/00
摘要： A lighting unit comprises a packaging substrate (10) formed from a semiconductor, a channel (12) formed in the substrate and a discrete light emitting diode arrangement (34) in the channel. A surface region of the channel comprises doped semiconductor layers (20, 24) which define a light sensor. The arrangement provides a light sensor (which can be used to determine colour and/or output flux) for a LED unit, with the light sensor embedded in substrate used for packaging. This provides a low cost integration process and provides good registration between the light sensor and the LED output.
摘要翻译： 照明单元包括由半导体形成的封装衬底（10），形成在衬底中的沟道（12）和沟道中的离散发光二极管装置（34）。 沟道的表面区域包括限定光传感器的掺杂半导体层（20,24）。 该装置提供用于LED单元的光传感器（其可以用于确定颜色和/或输出通量），其中光传感器嵌入用于包装的基板中。 这提供了低成本的集成过程，并且在光传感器和LED输出之间提供良好的配准。
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公开(公告)号：US20110103039A1
公开(公告)日：2011-05-05
申请号：US12922127
申请日：2009-03-09
CPC分类号： H05B33/10 , Y10T428/24298 , Y10T428/24331
摘要： The present invention relates to a luminescent component (30) and a manufacturing method thereof. The luminescent component (30) comprises a first transparent carrier (18), a second transparent carrier (24), a substrate (10) sandwiched between said transparent carriers (18; 24), the substrate (10) comprising a conduit from the first transparent layer (18) to the second transparent carrier (24), the conduit being filled with a luminescent solution (20). This facilitates the use of colloidal solutions of quantum dots in such a luminescent component (30). Preferably, the substrate (10) is direct bonded to the transparent carriers (18, 24) using direct wafer bonding techniques.
摘要翻译： 本发明涉及发光成分（30）及其制造方法。 发光组件（30）包括第一透明载体（18），第二透明载体（24），夹在所述透明载体（18; 24）之间的基底（10），所述基底（10） 透明层（18）连接到第二透明载体（24），导管填充有发光溶液（20）。 这有助于在这种发光组分（30）中使用量子点的胶体溶液。 优选地，使用直接晶片接合技术将衬底（10）直接接合到透明载体（18,24）。
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公开(公告)号：US20110006328A1
公开(公告)日：2011-01-13
申请号：US12864752
申请日：2009-01-27
CPC分类号： H01L25/167 , H01L31/105 , H01L31/153 , H01L33/486 , H01L2224/16225 , H01L2924/0002 , H05B33/0803 , H05B33/0866 , H01L2924/00
摘要： A lighting unit comprises a packaging substrate (10) formed from a semiconductor, a channel (12) formed in the substrate and a discrete light emitting diode arrangement (34) in the channel. A surface region of the channel comprises doped semiconductor layers (20,24) which define a light sensor. The arrangement provides a light sensor (which can be used to determine colour and/or output flux) for a LED unit, with the light sensor embedded in substrate used for packaging. This provides a low cost integration process and provides good registration between the light sensor and the LED output.
摘要翻译： 照明单元包括由半导体形成的封装衬底（10），形成在衬底中的沟道（12）和沟道中的离散发光二极管装置（34）。 通道的表面区域包括限定光传感器的掺杂半导体层（20,24）。 该装置提供用于LED单元的光传感器（其可以用于确定颜色和/或输出通量），其中光传感器嵌入用于包装的基板中。 这提供了低成本的集成过程，并且在光传感器和LED输出之间提供良好的配准。
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公开(公告)号：US08367552B2
公开(公告)日：2013-02-05
申请号：US10526422
申请日：2003-08-04
申请人： Roel Daamen , Viet Nguyen Hoang , Romano Julma Oscar Maria Hoofman , Greja Johanna Adriana Maria Verheijden
发明人： Roel Daamen , Viet Nguyen Hoang , Romano Julma Oscar Maria Hoofman , Greja Johanna Adriana Maria Verheijden
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/7684 , H01L21/7688
摘要： The present invention relates to a method for fabrication of in-laid metal interconnects. The method comprises the steps of providing a substrate with a dielectric material on top thereof, depositing a protection layer on top of the dielectric material, depositing a sacrificial layer on top of the protection layer, the sacrificial layer having a mechanical strength that is lower than the mechanical strength of the protection layer, making an opening) through the sacrificial layer, through the protection layer and into the dielectric material, depositing a barrier layer in the opening and on the sacrificial layer, depositing metal material on the barrier layer, the metal material filling the opening, removing portions of the metal material existing beyond the opening by means of polishing, and removing the barrier layer and the sacrificial layer in one polishing step.
摘要翻译： 本发明涉及一种内置金属互连的制造方法。 该方法包括以下步骤：在其顶部提供介电材料的基底，在电介质材料的顶部上沉积保护层，在保护层的顶部上沉积牺牲层，牺牲层的机械强度低于 保护层的机械强度，形成开口）穿过保护层并进入电介质材料，在开口和牺牲层上沉积阻挡层，在阻挡层上沉积金属材料，金属 填充开口的材料，通过抛光去除存在于开口之外的金属材料的部分，以及在一个抛光步骤中去除阻挡层和牺牲层。
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公开(公告)号：US08012872B2
公开(公告)日：2011-09-06
申请号：US11718876
申请日：2005-11-02
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/3212 , H01L21/7684 , H01L21/76865
摘要： Manufacturing a damascene structure involves: forming a sacrificial layer (20) on a substrate (10) to protect an area around a recess (30) for the damascene structure, forming a barrier layer (40) in the recess, and in electrical contact with the sacrificial layer, forming the damascene structure (50) in the recess, and planarizing. During the planarizing the sacrificial layer reacts electrochemically with the barrier layer or with the damascene structure. This can alter a relative rate of removal of the damascene structure and the sacrificial layer so as to reduce dishing or protrusion of the damascene structure, and reduce copper residues, and reduce barrier corrosion. The barrier layer can be formed by ALCVD. The barrier material being one or more of WCN and TaN. The sacrificial layer can be TaN, TiN or W.
摘要翻译： 制造镶嵌结构包括：在基底（10）上形成牺牲层（20）以保护用于镶嵌结构的凹部（30）周围的区域，在凹槽中形成阻挡层（40），并与 牺牲层，在凹部中形成镶嵌结构（50）并且平坦化。 在平坦化期间，牺牲层与阻挡层或镶嵌结构电化学反应。 这可以改变镶嵌结构和牺牲层的相对去除速率，以减少镶嵌结构的凹陷或凸起，并且减少铜残留物，并减少屏障腐蚀。 阻挡层可以通过ALCVD形成。 阻挡材料是WCN和TaN中的一种或多种。 牺牲层可以是TaN，TiN或W.
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公开(公告)号：US20110097896A1
公开(公告)日：2011-04-28
申请号：US10526422
申请日：2003-08-04
IPC分类号： H01L21/768
CPC分类号： H01L21/7684 , H01L21/7688
摘要： The present invention relates to a method for fabrication of in-laid metal interconnects. The method comprises the steps of providing a substrate with a dielectric material (1) on top thereof, depositing a protection layer (2) on top of the dielectric material, depositing a sacrificial layer (7) on top of the protection layer, the sacrificial layer having a mechanical strength that is lower than the mechanical strength of the protection layer, making an opening (3) through the sacrificial layer, through the protection layer and into the dielectric material, depositing a barrier layer (4) in the opening and on the sacrificial layer, depositing metal material (5) on the barrier layer, the metal material filling the opening, removing portions of the metal material existing beyond the opening by means of polishing, and removing the barrier layer and the sacrificial layer in one polishing step.
摘要翻译： 本发明涉及一种内置金属互连的制造方法。 该方法包括以下步骤：在其顶部提供介电材料（1）的基底，在电介质材料的顶部上沉积保护层（2），在保护层的顶部上沉积牺牲层（7） 具有低于保护层的机械强度的机械强度的层，通过保护层形成通过牺牲层的开口（3）并进入电介质材料，在开口中沉积阻挡层（4） 牺牲层，在阻挡层上沉积金属材料（5），填充开口的金属材料，通过抛光去除存在于开口之外的金属材料的部分，以及在一个抛光步骤中去除阻挡层和牺牲层 。
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28.发明申请公开(公告)号：US20090267234A1
公开(公告)日：2009-10-29
申请号：US12306032
申请日：2007-06-15
申请人： Viet Nguyen Hoang
发明人： Viet Nguyen Hoang
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5283 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： The invention relates to a semiconductor device comprising a substrate (1) and at least one interconnect layer located at a surface of the substrate (1), the interconnect layer comprising a first wire (20″) and a second wire (20′) which are located in the interconnect layer, the first wire (20″) having a first thickness (T1) and the second wire (20′having a second thickness (T2) that is different from the first thickness, the thickness (T1,T2) being defined in a direction perpendicular to said surface. The invention further relates to a method of manufacturing a semiconductor device comprising a substrate (1) and an interconnect layer located at a surface of the substrate (1), the interconnect layer comprising a first wire (20″) and a second wire (20) which are located in the interconnect layer.
摘要翻译： 本发明涉及一种半导体器件，其包括基片（1）和位于基片（1）表面的至少一个互连层，所述互连层包括第一线（20“）和第二线（20'）， 它们位于互连层中，第一线（20“）具有第一厚度（T1）和第二线（20'具有不同于第一厚度的第二厚度（T2），厚度（T1， 本发明还涉及一种制造半导体器件的方法，所述半导体器件包括衬底（1）和位于所述衬底（1）的表面处的互连层，所述互连层包括 第一线（20“）和第二线（20），其位于互连层中。
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公开(公告)号：US07025662B2
公开(公告)日：2006-04-11
申请号：US11197755
申请日：2005-08-03
摘要： The invention relates to an arrangement of a chemical-mechanical polishing tool for chemical-mechanical polishing a surface on a wafer, comprising a polishing pad (4), a drive unit (9), pressing means (6), a wafer holder (5), first dispensing means (7) and second dispensing means (8); the wafer holder for holding a wafer (W) being arranged at a holder location (L0); the pressing means (6) being arranged to press the wafer holder (5) to the polishing pad (4); the first dispensing means (7) for dispensing a first fluid on the polishing pad (4) being arranged at a first dispensing means location (L1); the second dispensing means (8) for dispensing a second fluid on the polishing pad (4) being arranged at a second dispensing means location (L2); the polishing pad (4) comprising a polishing surface for polishing the wafer (W), and the polishing pad (4) further being connected to the drive unit (9) for moving the polishing surface in a first direction (ω1) relative to the holder location (L0);wherein the first dispensing means location (L1) of the first dispensing means (7) is arranged in a downstream direction with respect to the holder location (L0) at a first downstream distance (d1), with the downstream direction being taken in relation to the first direction (ω1); and the second dispensing means location (L2) of the second dispensing means (8) is arranged in an upstream direction with respect to the holder location (L0) at a first upstream distance (d3), with the upstream direction being taken in relation to the first direction (ω1).The invention further relates to a method of chemical-mechanical polishing using such an arrangement.
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30.发明申请公开(公告)号：US20060128089A1
公开(公告)日：2006-06-15
申请号：US10539280
申请日：2003-12-15
IPC分类号： H01L21/8238
CPC分类号： H01L21/76828 , H01L21/76807 , H01L2221/1026
摘要： The invention relates to the manufacture of a semiconductor device (10) with a semiconductor body (1) and a substrate (2) and comprising at least one semiconductor element (3), which semiconductor device is equipped with at least one connection region (4) and a superjacent strip-shaped connection conductor (5) which is connected to the connection region, which connection region and connection conductor are both recessed in a dielectric, and a dielectric region (6) of a first material is provided on the semiconductor body (1) at the location of the connection region (4) to be formed, after which the dielectric region (6) is coated with a dielectric layer (7) of a second material that differs from the first material, which dielectric layer is provided, at the location of the strip-shaped connection conductor (5) to be formed, with a strip-shaped recess (7A) which overlaps the dielectric region (6) and extends up to said dielectric region, and after the formation of the recess (7A) and the removal of the dielectric region (6), the connection region (4) is formed by depositing an electroconductive material in the space (6A) created by the removal of the dielectric region (6), and the connection conductor (5) is formed by depositing an electroconductive material in the recess (7A). According to the invention, for the first material use is made of an organic material, and for the second material use is made of a material having a higher decomposition temperature than the organic material, and the dielectric region (6) is removed by heating it at a temperature above the decomposition temperature of the organic material yet below the decomposition temperature of the second material. A method according to the invention is very simple and, due to an optimal choice for the second material, may result in a high planarity of the device (10) obtained. For the dielectric region (4), use is preferably made of a photoresist, and for the dielectric layer (7), use is preferably made of a liquid material such as a SILK or SOG material which is converted to the solid state by heating.
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