公开(公告)号：US20070184621A1

公开(公告)日：2007-08-09

申请号：US11694225

申请日：2007-03-30

申请人： Dureseti Chidambarrao ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Lawrence Clevenger ,  Omer Dokumaci ,  Kaushik Kumar ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/7836 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76804 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6659

摘要： The present invention relates to an FET device having a conductive gate electrode with angled sidewalls. Specifically, the sidewalls of the FET device are offset from the vertical direction by an offset angle that is greater than about 0° and not more than about 45°. In such a manner, such conductive gate electrode has a top surface area that is smaller than its base surface area. Preferably, the FET device further comprises source/drain metal contacts that are also characterized by angled sidewalls, except that the offset angle of the source/drain metal contacts are arranged so that the top surface area of each metal contact is larger than its base surface area. The FET device of the present invention has significantly reduced gate to drain metal contact overlap capacitance, e.g., less than about 0.07 femtoFarads per micron of channel width, in comparison with conventional FET devices having straight-wall gate electrodes and metal contacts.

摘要翻译： 本发明涉及一种FET器件，其具有带有倾斜侧壁的导电栅电极。 具体来说，FET器件的侧壁从垂直方向偏移大于约0°且不大于约45°的偏移角。 以这种方式，这种导电栅电极具有小于其基表面积的顶表面积。 优选地，FET器件还包括源极/漏极金属触点，其特征还在于具有倾斜的侧壁，除了源极/漏极金属触点的偏移角度被布置成使得每个金属触点的顶表面积大于其基底表面 区。 与具有直壁栅电极和金属触点的常规FET器件相比，本发明的FET器件具有显着减小的栅极与漏极金属接触重叠电容，例如小于约0.07毫微微法每微米沟道宽度。

公开(公告)号：US20070092990A1

公开(公告)日：2007-04-26

申请号：US11163523

申请日：2005-10-21

申请人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

发明人： Michael Belyansky ,  Dureseti Chidambarrao ,  Lawrence Clevenger ,  Kaushik Kumar ,  Carl Radens

IPC分类号： H01L21/00 ,  H01L29/76

CPC分类号： H01L21/76804 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to an field effect transistor (FET) comprising an inverted source/drain metallic contact that has a lower portion located in a first, lower dielectric layer and an upper portion located in a second, upper dielectric layer. The lower portion of the inverted source/drain metallic contact has a larger cross-sectional area than the upper portion. Preferably, the lower portion of the inverted source/drain metallic contact has a cross-sectional area ranging from about 0.03 μm2 to about 3.15 μm2, and such an inverted source/drain metallic contact is spaced apart from a gate electrode of the FET by a distance ranging from about 0.001 μm to about 5 μm.

摘要翻译： 本发明涉及一种场效应晶体管（FET），其包括反向的源极/漏极金属接触，其具有位于第一下部电介质层中的下部和位于第二上部电介质层中的上部。 倒置的源极/漏极金属触点的下部具有比上部更大的横截面面积。 优选地，倒置的源极/漏极金属接触件的下部具有约0.03毫米2至约3.15微米的横截面积，并且这样的反相源 /漏极金属触点与FET的栅电极间隔约0.001μm至约5μm的距离。

公开(公告)号：US07064064B2

公开(公告)日：2006-06-20

申请号：US11058783

申请日：2005-02-16

申请人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

发明人： Shyng-Tsong Chen ,  Timothy J. Dalton ,  Kenneth M. Davis ,  Chao-Kun Hu ,  Fen F. Jamin ,  Steffen K. Kaldor ,  Mahadevaiyer Krishnan ,  Kaushik Kumar ,  Michael F. Lofaro ,  Sandra G. Malhotra ,  Chandrasekhar Narayan ,  David L. Rath ,  Judith M. Rubino ,  Katherine L. Saenger ,  Andrew H. Simon ,  Sean P. E. Smith ,  Wei-tsu Tseng

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76847 ,  H01L21/76883 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit structure is disclosed that has a layer of logical and functional devices and an interconnection layer above the layer of logical and functional devices. The interconnection layer has a substrate, conductive features within the substrate and caps positioned only above the conductive features.

摘要翻译： 公开了一种集成电路结构，其具有逻辑和功能器件层以及逻辑和功能器件层之上的互连层。 互连层具有衬底，衬底内的导电特征和仅位于导电特征之上的盖。

公开(公告)号：US20050040532A1

公开(公告)日：2005-02-24

申请号：US10645308

申请日：2003-08-21

申请人： Kaushik Kumar ,  Kelly Malone ,  Christy Tyberg

发明人： Kaushik Kumar ,  Kelly Malone ,  Christy Tyberg

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous low-k line level dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous low-k dielectric; a second thin non-porous low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

摘要翻译： 提供了一种双镶嵌互连结构，其具有在基板上的旋涂电介质的图案化多层。 该结构包括：基底上的旋涂电介质的图案化多层，包括：盖层; 第一无孔通孔级低k电介质层，其上具有带有底部和侧壁的金属通孔导体; 蚀刻停止层; 第一多孔低k线电介质层，其上具有底部和侧壁的金属线导体; 在第一多孔低k电介质上的抛光停止层; 用于涂覆和平坦化线和通孔侧壁的第二薄无孔低k介电层; 以及金属通孔和线路导体与电介质层之间的衬垫材料。 还提供了形成双镶嵌互连结构的方法。

公开(公告)号：US20090118852A1

公开(公告)日：2009-05-07

申请号：US12000061

申请日：2007-12-07

申请人： Kaushik Kumar ,  Sanat Kumar Mukherjee ,  Goutam Pohit

发明人： Kaushik Kumar ,  Sanat Kumar Mukherjee ,  Goutam Pohit

IPC分类号： G06F17/00 ,  G06G7/64

CPC分类号： G05B19/186 ,  G05B2219/49029 ,  G06F17/5009 ,  G06F17/5095 ,  G06F2217/12 ,  Y02P90/265

摘要： A software structure which when adapted in an apparatus is capable of virtual manufacturing of transmission elements for example gear means with chip formation, the software structure comprising a start module for loading the source file in a main editor-file that contains the computer program, an input module for providing input parameters that are essential for the configuration of a product and a cutting tool, a product design module for evolving the parameters for the manufacturing of the product; and a virtual manufacturing module having at least three sub-modules one each for tool generation, visualisation of machining operation, and disassembly of the product from the machine bed.

摘要翻译： 一种软件结构，当在设备中适配时，能够虚拟制造传输元件，例如具有芯片形成的齿轮装置，该软件结构包括用于将源文件加载到包含计算机程序的主编辑文件中的启动模块， 输入模块，用于提供对产品和切割工具的配置至关重要的输入参数，用于演化产品制造参数的产品设计模块; 以及具有至少三个子模块的虚拟制造模块，每个子模块各自用于工具生成，加工操作的可视化以及产品与机床的拆卸。

公开(公告)号：US20070111509A1

公开(公告)日：2007-05-17

申请号：US11619502

申请日：2007-01-03

申请人： Elbert Huang ,  Kaushik Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy Tyberg

发明人： Elbert Huang ,  Kaushik Kumar ,  Kelly Malone ,  Dirk Pfeiffer ,  Muthumanickam Sankarapandian ,  Christy Tyberg

IPC分类号： H01L21/4763

CPC分类号： H01L21/76801 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76835 ,  Y10S438/97

摘要： Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.08 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

摘要翻译： 本文描述了具有低介电常数的掩埋蚀刻停止层的互连结构和与产生这种掩埋蚀刻停止层有关的方法。 本发明的互连结构包括掩埋的蚀刻停止层，其由具有下列成分的聚合物材料构成：其中X 1，X，Y， 其中0.05 <= v <= 0.8,0 <= w <= 0.9,0.05 <= x <= 0.8,0 <= y <= 0.3,0.05 对于v + w + x + y + z = 1，z <= 0.08; 位于所述掩埋蚀刻停止层正下方的通孔层间电介质; 位于所述掩埋蚀刻停止层正上方的线级层间电介质; 以及导电穿过所述通孔级电介质，所述线级电介质和所述掩埋蚀刻停止层的金属特征。

公开(公告)号：US20070007244A1

公开(公告)日：2007-01-11

申请号：US11160671

申请日：2005-07-05

申请人： Habib Hichri ,  Kaushik Kumar ,  Helen Maynard

发明人： Habib Hichri ,  Kaushik Kumar ,  Helen Maynard

IPC分类号： G01L21/30 ,  H01L21/306 ,  C23F1/00 ,  B44C1/22

CPC分类号： G01M3/226 ,  H01J37/32623 ,  H01J37/32935 ,  H01L21/67069

摘要： A system and method for detecting a loss of plasma confinement. The system includes a plasma chamber that includes a plasma space and a non-plasma space. A plasma apparatus generates a plasma within the plasma space. The non-plasma space surrounds the plasma space and is separated from the plasma space by a confinement barrier that is adapted to confine the plasma in the plasma space during performance of an operational process by the plasma on a substrate disposed within the plasma space. Plasma detectors distributed on bounding surfaces of the non-plasma space are adapted to detect plasma that has escaped from the plasma space during performance of the operational process. The operational process is performed while the plasma detectors are monitoring the non-plasma space for a presence of the escaped plasma in the non-plasma space. If the monitoring has detected the escaped plasma, then the operational process is aborted.

摘要翻译： 一种用于检测血浆约束损失的系统和方法。 该系统包括等离子体室，其包括等离子体空间和非等离子体空间。 等离子体装置在等离子体空间内产生等离子体。 非等离子体空间围绕等离子体空间，并且通过限制屏障与等离子体空间分离，该限制屏障适于在等离子体在等离子体空间内的衬底上的等离子体执行操作过程期间将等离子体限制在等离子体空间中。 分布在非等离子体空间的边界表面上的等离子体检测器适于检测在执行操作过程期间已经从等离子体空间逸出的等离子体。 在等离子体检测器正在监测非等离子体空间以在非等离子体空间中存在逸出的等离子体的同时执行操作过程。 如果监测检测到逃逸的等离子体，则操作过程中止。

公开(公告)号：US07888252B2

公开(公告)日：2011-02-15

申请号：US12372174

申请日：2009-02-17

申请人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

发明人： Johnathan E. Faltermeier ,  Stephan Grunow ,  Kangguo Cheng ,  Kevin Petrarca ,  Kaushik Kumar ,  Lawrence A. Clevenger ,  Shom Ponoth ,  Vidhya Ramachandran

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76829

摘要： A method of forming contacts for semiconductor devices, the method including depositing an inter-level dielectric (ILD) over a plurality of gate stacks, in which the divots within the inter-level dielectric layer are defined by the spaces between the gate stacks, filling the divots with an initial fill material, depositing a masking material on the dielectric over the gate stacks, and selectively etching the fill material to form contact vias. The fill material may be a self-assembly material such as a multi-block copolymer in which the blocks self organize vertically within the divots, so that a selective etch of the block material will remove the vertically organized blocks from the divot, but leave at least one block over the gate regions. In another embodiment, the fill material may be a metal, and the masking material may be a parylene based polymer.

摘要翻译： 一种形成用于半导体器件的触点的方法，所述方法包括在多个栅极叠层之间沉积层间电介质（ILD），其中层间电介质层内的阴影由栅极堆叠之间的空间限定，填充 具有初始填充材料的图案，在栅极堆叠上的电介质上沉积掩模材料，并且选择性地蚀刻填充材料以形成接触孔。 填充材料可以是自组装材料，例如多嵌段共聚物，其中嵌段自由地在密封区内垂直组织，使得嵌段材料的选择性蚀刻将从竖纹中去除垂直组织的块，而是离开 在门区域上至少有一个块。 在另一个实施方案中，填充材料可以是金属，掩蔽材料可以是聚对二甲苯基聚合物。

公开(公告)号：US20080099923A1

公开(公告)日：2008-05-01

申请号：US11968929

申请日：2008-01-03

申请人： Kaushik Kumar ,  Kelly Malone ,  Christy Tyberg

发明人： Kaushik Kumar ,  Kelly Malone ,  Christy Tyberg

IPC分类号： H01L23/48

CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76835 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene interconnect structure having a patterned multilayer of spun-on dielectrics on a substrate is provided. The structure includes: a patterned multilayer of spun-on dielectrics on a substrate, including: a cap layer; a first non-porous via level low-k dielectric layer having thereon metal via conductors with a bottom portion and sidewalls; an etch stop layer; a first porous line level low-k dielectric layer having thereon metal line conductors with a bottom portion and sidewalls; a polish stop layer over the first porous line level low-k dielectric; a second thin non-porous via level low-k dielectric layer for coating and planarizing the line and via sidewalls; and a liner material between the metal via and line conductors and the dielectric layers. Also provided is a method of forming the dual damascene interconnect structure.

摘要翻译： 提供了一种双镶嵌互连结构，其具有在基板上的旋涂电介质的图案化多层。 该结构包括：基底上的旋涂电介质的图案化多层，包括：盖层; 第一无孔通孔级低k电介质层，其上具有带有底部和侧壁的金属通孔导体; 蚀刻停止层; 第一多孔线路电平低k电介质层，其上具有金属线导体，其具有底部和侧壁; 在第一多孔线路低k电介质上的抛光停止层; 第二薄的无孔通孔级低k电介质层，用于涂覆和平坦化线和通孔侧壁; 以及金属通孔和线路导体与电介质层之间的衬垫材料。 还提供了形成双镶嵌互连结构的方法。

公开(公告)号：US20060128163A1

公开(公告)日：2006-06-15

申请号：US10905065

申请日：2004-12-14

申请人： Shyng-Tsong Chen ,  Kaushik Kumar ,  Kelly Malone

发明人： Shyng-Tsong Chen ,  Kaushik Kumar ,  Kelly Malone

IPC分类号： H01L21/469

CPC分类号： H01L21/76802 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/3105 ,  H01L21/76831

摘要： Damaged porous OSG layers and other damage may be chemically healed. Chemical healing is particularly advantageous in a porous OSG layer in a sub 90 nm ILD. For example, chemical healing may be by reacting the damage with an adhesion promoter having a “k” value comparable to the “k” value desired in the damaged material. Damaged porous OSG layers (which are hydrophilic) may be manipulated to prevent them from allowing moisture to reach copper lines. Undesirable copper out-diffusion can be controlled in ILDs having porous OSG geometry.

摘要翻译： 受损的多孔OSG层和其他损伤可以化学愈合。 在90nm以下的ILD中，化学愈合特别有利于多孔OSG层。 例如，化学愈合可以通过使损伤与具有与损伤材料中所需的“k”值相当的“k”值的粘合促进剂反应。 可以操纵损坏的多孔OSG层（其是亲水的）以防止它们使水分达到铜线。 可以在具有多孔OSG几何形状的ILD中控制不希望的铜外扩散。