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    Non-volatile storage element having dual work-function electrodes
    21.
    发明授权
    Non-volatile storage element having dual work-function electrodes 有权
    具有双功能电极的非易失性存储元件

    公开(公告)号：US08829592B2

    公开(公告)日：2014-09-09

    申请号：US12967436

    申请日：2010-12-14

    申请人： Walid M. Hafez ,  Anisur Rahman

    发明人： Walid M. Hafez ,  Anisur Rahman

    IPC分类号： H01L29/788 ,  H01L29/423 ,  G11C16/04 ,  H01L29/792 ,  H01L49/02 ,  H01L29/51 ,  H01L21/28

    CPC分类号： H01L29/792 ,  G11C16/0466 ,  H01L21/28282 ,  H01L28/40 ,  H01L29/4234 ,  H01L29/513 ,  H01L45/00

    摘要： A non-volatile storage element and a method of forming the storage element. The non-volatile storage element comprises: a first electrode including a first material having a first work function; a second electrode including a second material having a second work function higher than the first work function; a first dielectric disposed between the first electrode and the second electrode, the first dielectric having a first bandgap; a second dielectric disposed between the first dielectric and the second electrode, the second dielectric having a second bandgap wider than the first bandgap and being disposed such that a quantum well is created in the first dielectric; and a third dielectric disposed between the first electrode and the first dielectric, the third dielectric being thinner than the second dielectric and having a third bandgap wider than the first bandgap.

    摘要翻译： 非易失性存储元件和形成存储元件的方法。 非易失性存储元件包括：第一电极，其包括具有第一功函数的第一材料; 第二电极，包括具有高于第一功函数的第二功函数的第二材料; 设置在所述第一电极和所述第二电极之间的第一电介质，所述第一电介质具有第一带隙; 设置在所述第一电介质和所述第二电极之间的第二电介质，所述第二电介质具有比所述第一带隙宽的第二带隙，并且被布置为使得在所述第一电介质中产生量子阱; 以及设置在所述第一电极和所述第一电介质之间的第三电介质，所述第三电介质比所述第二电介质薄，并且具有比所述第一带隙宽的第三带隙。

    Penetrating implant for forming a semiconductor device
    22.
    发明授权
    Penetrating implant for forming a semiconductor device 有权
    用于形成半导体器件的穿透植入物

    公开(公告)号：US08426927B2

    公开(公告)日：2013-04-23

    申请号：US13107783

    申请日：2011-05-13

    申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    IPC分类号： H01L29/66 ,  H01L21/02

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

    摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

    摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

    MEMORY CELL USING BTI EFFECTS IN HIGH-K METAL GATE MOS
    23.
    发明申请
    MEMORY CELL USING BTI EFFECTS IN HIGH-K METAL GATE MOS 有权
    在高K金属栅MOS中使用BTI效应的存储单元

    公开(公告)号：US20120163103A1

    公开(公告)日：2012-06-28

    申请号：US12976630

    申请日：2010-12-22

    申请人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

    发明人： Walid M. Hafez ,  Anisur Rahman ,  Chia-Hong Jan

    IPC分类号： G11C7/00

    CPC分类号： G11C7/00 ,  G11C17/16 ,  G11C17/18 ,  H03K19/173

    摘要： Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.

    摘要翻译： 公开了用于实现利用高k /金属栅极n型或p型金属氧化物半导体（NMOS或PMOS）晶体管的偏置温度不稳定性（BTI）效应的非易失性存储器的技术和电路。 例如，存储器或可编程逻辑电路的编程位单元表现出由用于编程位单元的应用编程偏置产生的阈值电压偏移。 在一些情况下，施加第一编程偏置使得器件具有第一状态，并且施加第二编程偏置使得器件具有与第一状态不同的第二状态。 可以通过施加相反的极性应力来擦除编程的位单元，并通过多个周期重新编程。 根据一些实施例，位单元配置可以与列/行选择电路和/或读出电路结合使用。

    Fin-based semiconductor devices and methods
    26.
    发明授权
    Fin-based semiconductor devices and methods 有权

    公开(公告)号：US10002954B2

    公开(公告)日：2018-06-19

    申请号：US15100286

    申请日：2014-01-24

    申请人： Walid M. Hafez ,  Chia-Hong Jan

    发明人： Walid M. Hafez ,  Chia-Hong Jan

    IPC分类号： H01L29/66 ,  H01L29/74 ,  H01L29/417 ,  H01L29/06 ,  H01L27/02 ,  H01L21/225 ,  H01L29/78

    CPC分类号： H01L29/74 ,  H01L21/2255 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/41716 ,  H01L29/66363 ,  H01L29/785

    摘要： Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.

    HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS
    28.
    发明申请
    HIGH VOLTAGE THREE-DIMENSIONAL DEVICES HAVING DIELECTRIC LINERS 有权
    具有电介质衬底的高电压三维器件

    公开(公告)号：US20150179525A1

    公开(公告)日：2015-06-25

    申请号：US14641117

    申请日：2015-03-06

    申请人： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

    发明人： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

    IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

    CPC分类号： H01L27/1211 ,  H01L21/02164 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02598 ,  H01L21/28158 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/845 ,  H01L29/42356 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

    摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

    摘要翻译： 描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。 例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。 第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。 第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。 第一栅极电介质由设置在第一鳍状物活性区域上并沿着第一间隔物的侧壁的第一介电层和设置在第一介电层上并沿着第一间隔物的侧壁的第二不同介电层组成。 半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。 第二栅极结构包括第二栅极电介质，第二栅电极和第二间隔物。 第二栅极电介质由设置在第二鳍状物活性区域和第二间隔物的侧壁上的第二介电层构成。

    PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE
    30.
    发明申请
    PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE 有权
    非平面半导体器件结构精密电阻器

    公开(公告)号：US20140084381A1

    公开(公告)日：2014-03-27

    申请号：US13625698

    申请日：2012-09-24

    申请人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

    发明人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

    IPC分类号： H01L27/06 ,  H01L21/02

    CPC分类号： H01L21/823431 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/66795

    摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

    摘要翻译： 描述了用于非平面半导体器件结构的精密电阻器。 在第一示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。 电阻器结构设置在第一半导体鳍片上方，但不在第二半导体鳍片之上。 晶体管结构由第二半导体鳍形成，但不由第一半导体鳍形成。 在第二示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。 隔离区设置在基板之上，位于第一和第二半导体鳍之间，并且在小于第一和第二半导体鳍片的高度处。 电阻结构设置在隔离区域上方，但不在第一和第二半导体鳍片之上。 第一和第二晶体管结构分别由第一和第二半导体鳍形成。