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    Internal voltage monitoring for integrated circuit devices
    22.
    发明授权
    Internal voltage monitoring for integrated circuit devices 有权

    公开(公告)号：US09804207B1

    公开(公告)日：2017-10-31

    申请号：US15058014

    申请日：2016-03-01

    Applicant: Xilinx, Inc.

    Inventor： Austin H. Lesea

    IPC: G01R31/00 ,  G01R31/3187 ,  G01R19/252 ,  G01R31/28

    CPC classification number: G01R19/252 ,  G01R19/2509 ,  G01R31/2879

    Abstract: An integrated circuit (IC) is located on an IC chip and includes an integrated voltage regulator circuit that provides an internal supply voltage to the IC. A test mode signal can be received from an external pin of the IC chip. In response to the test mode signal, the IC can enter a test mode where the internal supply voltage is provided to components of the IC. Also in the test mode, voltage characteristics of the internal supply voltage are measured to produce an analog held value. The measurements occur in an analog domain and over a plurality of sample-and-hold windows. Upon completion of a measurement window, the analog held is converted to a digital value. The digital value is then stored in a memory circuit. The digital value is provided from the memory circuit to a reader device external to the IC.

    Dynamic voltage scaling in programmable integrated circuits
    24.
    发明授权
    Dynamic voltage scaling in programmable integrated circuits 有权
    可编程集成电路中的动态电压缩放

    公开(公告)号：US09231591B1

    公开(公告)日：2016-01-05

    申请号：US14568899

    申请日：2014-12-12

    Applicant: Xilinx, Inc.

    Inventor： Austin H. Lesea

    IPC: H03K19/173 ,  H03K19/00 ,  H03K19/08

    CPC classification number: H03K19/0016 ,  G06F1/28 ,  G06F1/3296 ,  G06F11/3062 ,  H03K3/0375 ,  H03K19/08 ,  Y02D10/172

    Abstract: An apparatus includes a first programmable circuit block including a plurality of programmable circuit elements. The plurality of programmable circuit elements include a hardwired, instrumented memory element. The instrumented memory element includes a first flip-flop configured to receive a data signal, a delay circuit configured to generate a delayed version of the data signal, and a second flip-flop identical to the first flip-flop and configured to receive the delayed version of the data signal. The instrumented memory element also may include a comparator configured to compare an output signal from the first flip-flop and an output signal from the second flip-flop and an error signal generator. The error signal generator is configured to generate an error signal responsive to a mismatch of bits between the output signal from the first flip-flop and the output signal from the second flip-flop.

    Abstract translation: 一种装置包括包括多个可编程电路元件的第一可编程电路块。 多个可编程电路元件包括硬接线的仪表存储元件。 仪表存储元件包括被配置为接收数据信号的第一触发器，被配置为产生数据信号的延迟版本的延迟电路，以及与第一触发器相同的第二触发器，并且被配置为接收延迟的 版本的数据信号。 仪表存储元件还可以包括比较器，其被配置为比较来自第一触发器的输出信号和来自第二触发器的输出信号和误差信号发生器。 误差信号发生器被配置为响应于来自第一触发器的输出信号和来自第二触发器的输出信号之间的位的失配而产生误差信号。

    OPTICAL COMMUNICATION CIRCUITS
    25.
    发明申请
    OPTICAL COMMUNICATION CIRCUITS 有权
    光通信电路

    公开(公告)号：US20150358085A1

    公开(公告)日：2015-12-10

    申请号：US14297535

    申请日：2014-06-05

    Applicant: Xilinx, Inc.

    Inventor： Stephen M. Trimberger ,  Austin H. Lesea

    IPC: H04B10/50 ,  H04B10/548

    CPC classification number: H04B10/503 ,  H04B10/5161 ,  H04B10/548

    Abstract: Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations an optical transmitter includes an optical data port configured to engage an optical fiber. The optical transmitter also includes a plurality of lasers coupled to the optical data port and configured and arranged to transmit respective optical signals over the optical fiber via the optical data port when selected. A control circuit of the optical transmitter is configured to receive an input data signal and encode the input data signal for transmission over the optical fiber by selecting one or more of the plurality of lasers at a time. The control circuit is configured to select one or more of the plurality of lasers at a time according to one of a frequency modulation encoding algorithm or an amplitude modulation encoding algorithm.

    Abstract translation: 公开了用于光通信的各种装置，电路，系统和方法。 在一些实现中，光发射机包括被配置为接合光纤的光学数据端口。 光发射机还包括耦合到光数据端口的多个激光器，并被配置和布置成当选择时通过光数据端口在光纤上传输相应的光信号。 光发射器的控制电路被配置为接收输入数据信号，并且通过选择一次中的多个激光器中的一个或多个来编码输入数据信号以在光纤上传输。 控制电路被配置为根据频率调制编码算法或幅度调制编码算法之一来一次选择多个激光器中的一个或多个。

    Anti-spoofing of neural networks
    26.
    发明授权
    Anti-spoofing of neural networks 有权

    公开(公告)号：US11481615B1

    公开(公告)日：2022-10-25

    申请号：US16036631

    申请日：2018-07-16

    Applicant: Xilinx, Inc.

    Inventor： Austin H. Lesea

    IPC: G06N3/08 ,  G06T5/10 ,  G06N3/063

    Abstract: Anti-spoofing of a deep learning neural network may include receiving, by an artificial neural network implemented in hardware, an image and multi-dimensional spatial frequency data for the image. The artificial neural network is trained using training images and multi-dimensional spatial frequency data for the training images. Using the artificial neural network, a classification for an object in an image is determined based on the image and the multi-dimensional spatial frequency data for the image.

    Lateral cooling for multi-chip packages
    27.
    发明授权
    Lateral cooling for multi-chip packages 有权

    公开(公告)号：US10147666B1

    公开(公告)日：2018-12-04

    申请号：US14449052

    申请日：2014-07-31

    Applicant: Xilinx, Inc.

    Inventor： Stephen M. Trimberger ,  Austin H. Lesea

    IPC: H05K7/20 ,  G06F1/20 ,  H01L23/467 ,  H01L33/64 ,  H01L31/024 ,  H01S5/024 ,  H01L23/473 ,  H01L23/544 ,  H01L23/00

    Abstract: A method and apparatus are provided that includes an electronic device, a chip package and a method for cooling a chip package in an electronic device. In one example, the chip package includes an interposer or package substrate having a first IC die and a second IC die mounted thereon. The second IC die has a maximum safe operating temperature that is greater than a maximum safe operating temperature of the first IC die. An indicia is disposed on the chip package. The indicia designates an installation orientation of the interposer or package substrate which positions the first IC die upstream of the second IC die relative to a direction of cooling fluid flow.

    Architecture for silicon photonics enabling wafer probe and test
    28.
    发明授权
    Architecture for silicon photonics enabling wafer probe and test 有权

    公开(公告)号：US10042131B1

    公开(公告)日：2018-08-07

    申请号：US15480277

    申请日：2017-04-05

    Applicant: Xilinx, Inc.

    Inventor： Austin H. Lesea

    IPC: G02B6/12 ,  G02B6/42 ,  G02B6/124 ,  G02B6/125 ,  G02B6/13

    Abstract: Embodiments herein describe techniques for testing or aligning optical components in a photonic chip using a grating coupler. In one embodiment, the photonic chip may include an edge coupler and a grating coupler for optically coupling the photonic chip to external fiber optic cables. The edge coupler may be disposed on a side or edge of the photonic chip while the grating coupler is located on a top or side of the photonic chip. During fabrication, the edge coupler may be inaccessible. Instead of using the edge coupler to test the photonic chip, a testing apparatus can use the grating coupler along with a splitter to transfer optical test signals between an optical component in the photonic chip (e.g., a modulator or detector) and a test probe optically coupled to the grating coupler.

    Circuit for and method of routing data between die of an integrated circuit
    29.
    发明授权
    Circuit for and method of routing data between die of an integrated circuit 有权

    公开(公告)号：US10038647B1

    公开(公告)日：2018-07-31

    申请号：US15154892

    申请日：2016-05-13

    Applicant: Xilinx, Inc.

    Inventor： Austin H. Lesea

    IPC: H04L12/933 ,  H04L25/02

    CPC classification number: H04L49/109 ,  H04L25/0272 ,  H04L49/15

    Abstract: A circuit for routing data between die of an integrated circuit is described. The circuit comprises differential transmitter and receiver pairs of different integrated circuit die that are coupled together by differential transmission lines. A separate differential transmitter associated with the first die of the integrated circuit and a separate differential receiver associated with the second die of the integrated circuit are configured to transmit data day way of the differential transmission lines associated with the differential transmitter and receiver pairs.

    Adaptive optical channel compensation
    30.
    发明授权
    Adaptive optical channel compensation 有权

    公开(公告)号：US10038503B2

    公开(公告)日：2018-07-31

    申请号：US14459070

    申请日：2014-08-13

    Applicant: Xilinx, Inc.

    Inventor： Austin H. Lesea ,  Stephen M. Trimberger

    IPC: H04B10/12 ,  H04B10/00 ,  H04B10/04 ,  H04B10/2507 ,  H04B10/2575 ,  H04B10/07 ,  H04B10/58

    CPC classification number: H04B10/2507 ,  H04B10/07 ,  H04B10/2575 ,  H04B10/58

    Abstract: In an adaptation module relating generally to adaptive optical channel compensation, an analysis module is coupled to receive a first data signal and a second data signal and coupled to provide first information and second information. A comparison module is coupled to compare the first information and the second information to provide third information. An adjustment module is coupled to receive the third information to provide fourth information to compensate for distortion in the second data signal with reference to the first data signal. The second data signal is associated with a conversion of the first data signal to an optical signal for communication via an optical channel.

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