公开(公告)号：US5774410A

公开(公告)日：1998-06-30

申请号：US916010

申请日：1997-08-21

申请人： Yasunobu Nakase

发明人： Yasunobu Nakase

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C7/12 ,  G11C8/10 ,  G11C8/16 ,  G11C11/412 ,  G11C11/419 ,  G11C8/00

CPC分类号： G11C7/1075 ,  G11C11/412 ,  G11C11/419 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/12 ,  G11C8/10 ,  G11C8/16

摘要： It is an object to obtain a semiconductor storage device with two-port structure enabling reduction in circuit area. A crossbar switch CBS.sub.-- i (i=1-5) outputs a control signal for a zeroth port PORT.sub.-- 0 from an output portion CS.sub.-- i0 and outputs a control signal for a first port PORT.sub.-- 1 from an output portion CS.sub.-- i1 when a port exchange signal PSEL is at an L level, and outputs a control signal for the zeroth port PORT.sub.-- 0 from the output portion CS.sub.-- i1 and outputs a control signal for the first port PORT.sub.-- 1 from the output portion CS.sub.-- i0 when the port exchange signal PSEL is at an H level, thereby performing a port switching operation.

摘要翻译： 本发明的目的是获得具有能够减小电路面积的双端口结构的半导体存储装置。 交叉开关CBS-i（i = 1-5）从输出部分CS-i0输出第0端口PORT-0的控制信号，并从输出部分CS-i1输出第一端口PORT-1的控制信号 当端口交换信号PSEL为L电平时，从输出部CS-i1输出第0端口PORT-0的控制信号，并从输出部CS-i0输出第1端口PORT-1的控制信号 当端口交换信号PSEL处于H电平时，由此执行端口切换操作。

公开(公告)号：US5508966A

公开(公告)日：1996-04-16

申请号：US387636

申请日：1995-02-13

申请人： Yasunobu Nakase

发明人： Yasunobu Nakase

IPC分类号： G11C11/416 ,  G11C7/06 ,  H03K5/02 ,  G11C7/02

CPC分类号： G11C7/062

摘要： In order to increase the speed, reduce the number of components and lower power consumption in a sense amplifier circuit for reading data held in a selected memory cell, current difference appearing on a data line is converted to potential difference directly by a current mirror circuit in accordance with data held in a selected memory cell. This current mirror circuit includes a diode for clamping the potential of the data line, and a transistor which is connected with this diode in a current mirror arrangement. A sense current flows through the diode in accordance with the data held in the selected memory cell, a corresponding current flows through the transistor by a current mirror operation, and the sense current is monitored. The monitored sense current is converted to a voltage signal indicating data of the selected memory cell.

摘要翻译： 为了提高速度，减少组件数量并降低读出放大器电路中用于读取保存在所选择的存储单元中的数据的功率消耗，出现在数据线上的电流差异直接由电流镜像电路转换为电位差 根据保存在所选择的存储单元中的数据。 该电流镜电路包括用于钳位数据线的电位的二极管，以及以该电流反射镜布置与该二极管连接的晶体管。 感测电流根据保存在所选择的存储单元中的数据流过二极管，相应的电流通过电流镜操作流过晶体管，并且监测感测电流。 监视的感测电流被转换成指示所选存储单元的数据的电压信号。

公开(公告)号：US5365123A

公开(公告)日：1994-11-15

申请号：US937095

申请日：1992-08-31

申请人： Yasunobu Nakase ,  Hiroshi Makino ,  Kimio Ueda

发明人： Yasunobu Nakase ,  Hiroshi Makino ,  Kimio Ueda

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K19/013 ,  H03K19/017 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/08 ,  H03K19/0948 ,  H03K19/01

CPC分类号： H03K19/0948 ,  H03K19/013 ,  H03K19/01707 ,  H03K19/017518 ,  H03K19/018521

摘要： A CMOS gate circuit constituting the input stage of a semiconductor logic circuit includes a p channel MOS transistor supplied with current from a first power supply potential Vdd for charging an output signal line to a high level potential, a diode provided between MOS transistor and output signal line, an n channel MOS transistor supplied with current from a second power supply potential Vss responsive to an input signal (Vin) for discharging the potential of output signal line, and a diode provided between MOS transistor and output signal line. An input signal potential applied to input stage has its logic amplitude set to be Vdd-Vf to Vf. Vf represents the forward voltage of the diodes and the second power supply potential is set to be ground potential GND. The input signal potential has its logic amplitude limited, current flows through the diodes in its steady state, and, therefore, the logic amplitude of the signal potential Vout of output signal line becomes Vdd-Vf to Vf.

摘要翻译： 构成半导体逻辑电路的输入级的CMOS栅极电路包括从第一电源电位Vdd提供电流的ap沟道MOS晶体管，用于将输出信号线充电至高电平电位; MOS晶体管和输出信号线之间的二极管 ，n沟道MOS晶体管，响应于用于放电输出信号线的电位的输入信号（Vin）和从MOS晶体管和输出信号线之间提供的二极管，从第二电源电位Vss提供电流。 施加到输入级的输入信号电位的逻辑幅度设定为Vdd-Vf至Vf。 Vf表示二极管的正向电压，第二电源电位设为地电位GND。 输入信号电位的逻辑幅度受限，电流流过二极管处于稳定状态，输出信号线信号电位Vout的逻辑幅度变为Vdd-Vf至Vf。

公开(公告)号：US4792923A

公开(公告)日：1988-12-20

申请号：US901745

申请日：1986-08-29

申请人： Yasunobu Nakase ,  Kenji Anami

发明人： Yasunobu Nakase ,  Kenji Anami

IPC分类号： G11C5/00 ,  G11C11/411 ,  G11C11/415 ,  G11C7/00 ,  G11C11/40

CPC分类号： G11C5/005 ,  G11C11/4116 ,  G11C11/415

摘要： A semiconductor memory device having a plurality of word line pairs and drain lines, a plurality of bit line pairs, and a plurality of memory cells connected to both of the word line pairs and the bit line pairs at the cross points thereof, comprising: a first and a second word line provided as the word line pair, a memory cell including a first and a second multi-emitter transistor whose commonly connected emitters are connected to the drain line, first and second resistors where one of their ends are connected between the collectors of the first and second multi-emitter transistors respectively, and where their other ends are both connected to the first word line and the bases of the second and first multi-emitter transistors are connected to the other's collectors, respectively, and first and second diodes such as Schottky barrier diodes are connected between the collectors of the first and second multi-emitter transistors and the second word line, respectively. A current which is provided for each row which consists of an input transistor which receives an address input signal at its base input and a reference transistor which receives a predetermined voltage at its base input with the emitters thereof being commonly connected with each other. Third and fourth resistors are serially connected between the collector of the input transistor and a power supply voltage. A first word line driving transistor for driving the first word line whose base is connected between the third resistor and the fourth resistor and whose emitter is connected to the first word line. A second word line driving transistor for driving the second word line whose base is connected between the collector of the input transistor and the fourth resistor and whose emitter is connected to the second word line. The collectors of the first and the second word line driving transistor are connected to the voltage power supply.

摘要翻译： 一种半导体存储器件，具有多个字线对和漏极线，多个位线对和连接到其交叉点处的字线对和位线对的多个存储单元，包括： 设置为字线对的第一和第二字线;存储单元，包括共同连接的发射极连接到漏极线的第一和第二多发射极晶体管，第一和第二电阻的一端连接在漏极线之间 第一和第二多发射极晶体管的集电极分别连接到第一字线，第二和第二多发射极晶体管的基极分别连接到另一个集电极，第一和第二 诸如肖特基势垒二极管的二极管分别连接在第一和第二多发射极晶体管和第二字线的集电极之间。 为每行提供的电流由输入晶体管构成，该输入晶体管在其基极输入端接收地址输入信号，而基准晶体管在其基极输入端接收与其发射极的预定电压相互共同连接。 第三和第四电阻串联连接在输入晶体管的集电极和电源电压之间。 第一字线驱动晶体管，用于驱动第一字线，其基极连接在第三电阻和第四电阻之间，其发射极连接到第一字线。 第二字线驱动晶体管，用于驱动第二字线，其基极连接在输入晶体管的集电极和第四电阻之间，其发射极连接到第二字线。 第一和第二字线驱动晶体管的集电极连接到电压电源。

公开(公告)号：US08810229B2

公开(公告)日：2014-08-19

申请号：US13615069

申请日：2012-09-13

申请人： Yasunobu Nakase ,  Toru Goda

发明人： Yasunobu Nakase ,  Toru Goda

IPC分类号： H02M3/156

CPC分类号： H02M3/156 ,  H02M1/32

摘要： In a DC/DC converter, a control circuit determines an upper limit value of an inductor current based on a load current and an input dc voltage, and changes at least one of an on time and an off time of a switching element in such a manner that the detected inductor current does not exceed the upper limit value.

摘要翻译： 在DC / DC转换器中，控制电路基于负载电流和输入直流电压来确定电感器电流的上限值，并且改变这样的开关元件的导通时间和关断时间中的至少一个 检测电感电流不超过上限值的方式。

公开(公告)号：US06771109B2

公开(公告)日：2004-08-03

申请号：US10315940

申请日：2002-12-11

申请人： Yasunobu Nakase

发明人： Yasunobu Nakase

IPC分类号： H03L500

CPC分类号： H03K19/00384

摘要： Core circuitry is configured with a transistor formed of a gate oxide film of a thin film thickness, receiving a first power supply voltage to operate. Interface circuitry is configured with a transistor formed of a gate oxide film of a thick film thickness, receiving a second power supply voltage to operate. An appropriate voltage is supplied to the substrate of a P channel MOS transistor and an N channel MOS transistor which are output drivers, based on a mode select signal set according to the voltage level of the second power supply voltage, whereby a PNP parasitic bipolar transistor and an NPN parasitic bipolar transistor are driven at high speed. Although the interface circuitry of a semiconductor device is configured with a transistor formed of a thick gate oxide film, the speed will not be degraded even if the power supply voltage is set at a low voltage level.

摘要翻译： 核心电路配置有由薄膜厚度的栅极氧化膜形成的晶体管，接收第一电源电压以进行操作。 接口电路由具有厚膜厚度的栅极氧化膜形成的晶体管构成，接收第二电源电压进行工作。 基于根据第二电源电压的电压电平设定的模式选择信号，将适当的电压提供给作为输出驱动器的P沟道MOS晶体管和N沟道MOS晶体管的衬底，由此PNP寄生双极晶体管 并且高速驱动NPN寄生双极晶体管。 虽然半导体器件的接口电路配置有由厚栅氧化膜形成的晶体管，但是即使将电源电压设置在低电压电平，速度也不会降低。

公开(公告)号：US06201758B1

公开(公告)日：2001-03-13

申请号：US09499044

申请日：2000-02-07

申请人： Chikayoshi Morishima ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Niichi Itoh

发明人： Chikayoshi Morishima ,  Yasunobu Nakase ,  Tetsuya Watanabe ,  Niichi Itoh

IPC分类号： G11C800

CPC分类号： G11C11/419

摘要： A precharge circuit and a bit line load circuit are provided to a read bit line pair. The bit line load circuit continuously supplies a prescribed current to a read bit line. When data is written to one of memory cells selected in common by one read word line, the level of each read bit line will not be lowered to the level of the ground potential by the bit line load circuit if a read word line is activated, and therefore the loads of both discharge and charge operations by transistors in the memory cell are reduced.

摘要翻译： 向读位线对提供预充电电路和位线负载电路。 位线负载电路将规定的电流连续地提供给读位线。 当将数据写入一个读取字线共同选择的存储器单元之一时，如果读取的字线被激活，则每个读取位线的电平将不会被位线负载电路降低到地电位的电平， 因此减小存储单元中的晶体管的放电和充电操作的负载。

公开(公告)号：US5793222A

公开(公告)日：1998-08-11

申请号：US654204

申请日：1996-05-28

申请人： Yasunobu Nakase

发明人： Yasunobu Nakase

IPC分类号： H03K19/0175 ,  H03K5/01 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0948 ,  H03K17/16

CPC分类号： H03K19/00361 ,  H03K5/01

摘要： An input circuit of an input-output device has a waveform shaping function to relieve waveform distortion at an input-output line so that the upper bound of an operating frequency is enhanced while keeping sufficiently high and low signal levels. A signal waveform given to the input-output line is shaped by an inverter and transmitted as an input signal to an internal circuit. When receiving a signal, the input circuit of the input-output device uses a feedforward operation on the signal applied to the input-output line so as to shape the signal present on the input-output line. A period for the feedforward operation is determined by the delay time of a delay element.

摘要翻译： 输入输出装置的输入电路具有波形整形功能，以减轻输入 - 输出线处的波形失真，使得在保持足够高和低信号电平的同时增强工作频率的上限。 给输入输出线的信号波形由逆变器整形，作为输入信号发送到内部电路。 当输入输出装置的输入电路接收到信号时，对施加到输入 - 输出线路的信号使用前馈操作，以对输入 - 输出线路上存在的信号进行整形。 用于前馈操作的周期由延迟元件的延迟时间确定。

公开(公告)号：US5565796A

公开(公告)日：1996-10-15

申请号：US533722

申请日：1995-09-26

申请人： Yasunobu Nakase

发明人： Yasunobu Nakase

IPC分类号： G06F3/00 ,  G06F13/40 ,  G11C11/409 ,  H03K19/0175 ,  H03K19/0944 ,  H03R17/16

CPC分类号： G06F13/4077 ,  Y02B60/1228 ,  Y02B60/1235

摘要： To obtain a bus system capable of saving power consumption without increasing the number of data lines. In precharge period, by charging and discharging by data line drive circuits (23p, 23n), potentials of data lines (30, 31) of a bus (1) are set to power source potential (VDD) and grounding potential (GND), respectively. In equalizing period, by connecting the data lines (30, 31) by a switch (3), the potentials of the data lines (30, 31) are set to an intermediate potential of the power source potential (VDD) and grounding potential (GND). In data transfer period, by selectively connecting between data line (3) and power source line, and between data line (31) and grounding line, by means of data line drive circuits (23p, 23n), the signals transmitted through the data lines (30, 31) are caused to swing between the intermediate potential and power source potential (VDD), and between the intermediate potential and grounding potential (GND). A receiver circuit (25) converts the transmitted signal into a signal swinging between the power source potential (VDD) and grounding potential (GND).

摘要翻译： 获得能够节省功耗而不增加数据线数量的总线系统。 在预充电期间，通过数据线驱动电路（23p，23n）的充放电，总线（1）的数据线（30,31）的电位被设定为电源电位（VDD）和接地电位（GND） 分别。 在均衡期间，通过将数据线（30,31）与开关（3）连接，将数据线（30,31）的电位设定为电源电位（VDD）和接地电位（ GND）。 在数据传输期间，通过数据线（3）与电源线之间以及数据线（31）与接地线之间的选择性连接，借助于数据线驱动电路（23p，23n），通过数据线 （30,31）在中间电位和电源电位（VDD）之间以及中间电位和接地电位（GND）之间摆动。 接收器电路（25）将发送的信号转换成在电源电位（VDD）和接地电位（GND）之间摆动的信号。

公开(公告)号：US5428302A

公开(公告)日：1995-06-27

申请号：US52200

申请日：1993-04-22

申请人： Yasunobu Nakase

发明人： Yasunobu Nakase

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H03K19/08 ,  H03K19/0944 ,  H03K19/20 ,  H03K19/01

CPC分类号： H03K19/09448

摘要： A semiconductor logic circuit apparatus includes a plurality of logic circuits each including complementary field effect transistors, and a plurality bipolar transistors associated with the respective ones of the logic circuits. When any one of the outputs of the logic circuits becomes high, an associated bipolar transistor becomes conductive to cause an output terminal of the apparatus to be charged from a voltage supply. With all the outputs of the logic circuits being low, all of the bipolar transistors are non-conductive, and a current supply coupled between the output terminal and ground dicharges charge on the output terminal.

摘要翻译： 半导体逻辑电路装置包括多个逻辑电路，每个逻辑电路各自包括互补的场效应晶体管，以及与各个逻辑电路相关联的多个双极晶体管。 当逻辑电路的任何一个输出变高时，相关联的双极晶体管导通，从而使得装置的输出端子从电压源充电。 在逻辑电路的所有输出为低电平的情况下，所有双极晶体管都是非导通的，并且耦合在输出端子和接地之间的电流供电在输出端子上充电。