公开(公告)号：US07746682B2

公开(公告)日：2010-06-29

申请号：US11591881

申请日：2006-11-02

Applicant: Antonietta Oliva ,  Vei-Han Chan

Inventor： Antonietta Oliva ,  Vei-Han Chan

IPC: G11C11/00

CPC classification number: G11C11/4125 ,  B82Y10/00 ,  G11C5/005 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/025 ,  G11C14/009

Abstract: Apparatus and methods for reducing single-event upsets (SEUs) in latch-based circuitry (e.g., static random access memory (SRAM) cells) and other digital circuitry. According to an exemplary embodiment, a latch-based circuit includes a radiation-hardened latch having first and second cross-coupled inverters and first and second programmable resistance devices (PRDs). The first PRD is coupled between the output of the first inverter and the input of the second inverter. The second PRD is coupled between the output of the second inverter and the input of the first inverter. The PRDs may be programmed to low or high-resistance states. When SET to a low-resistance state, the latch of the latch-based circuitry may be accessed to read the current logic state stored by the latch or to write a new logic state into the latch. When RESET to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from generating SEUs.

Abstract translation: 用于减少基于锁存器的电路（例如，静态随机存取存储器（SRAM）单元）中的单事件故障（SEU）和其它数字电路的装置和方法。 根据示例性实施例，基于锁存器的电路包括具有第一和第二交叉耦合的反相器以及第一和第二可编程电阻器件（PRD）的辐射硬化锁存器。 第一PRD耦合在第一反相器的输出和第二反相器的输入之间。 第二PRD耦合在第二反相器的输出和第一反相器的输入之间。 PRD可以被编程为低电阻或高电阻状态。 当SET设置为低电阻状态时，可以访问基于锁存器的电路的锁存器以读取锁存器存储的当前逻辑状态或者将新的逻辑状态写入锁存器。 当RESET为高电阻状态时，锁存器处于辐射硬状态，从而防止锁存器产生SEU。

公开(公告)号：US20100091560A1

公开(公告)日：2010-04-15

申请号：US12459917

申请日：2009-07-09

Applicant: Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derharcobian ,  Vei-Han Chan

Inventor： Louis Charles Kordus, II ,  Antonietta Oliva ,  Narbeh Derharcobian ,  Vei-Han Chan

IPC: G11C11/56

CPC classification number: H01L45/1226 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1683 ,  H03K19/02

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

Abstract translation: 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，该相变材料的导电性可以根据施加到控制电极的控制信号进行修改。 这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。 因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。 这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

公开(公告)号：US20070235707A1

公开(公告)日：2007-10-11

申请号：US11811077

申请日：2007-06-07

Applicant: Louis Kordus ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

Inventor： Louis Kordus ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

IPC: H01L45/00

CPC classification number: H01L45/1226 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1683 ,  H03K19/02

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

Abstract translation: 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其中导电性可以根据施加到控制电极的控制信号进行修改。 这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。 因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。 这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。

公开(公告)号：US20070096071A1

公开(公告)日：2007-05-03

申请号：US11267788

申请日：2005-11-03

Applicant: Louis Kordus ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

Inventor： Louis Kordus ,  Antonietta Oliva ,  Narbeh Derhacobian ,  Vei-Han Chan

IPC: H01L29/02

CPC classification number: H01L45/1226 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/126 ,  H01L45/1683 ,  H03K19/02

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

公开(公告)号：US07122415B2

公开(公告)日：2006-10-17

申请号：US10243379

申请日：2002-09-12

Applicant: Chuck Jang ,  Zhong Dong ,  Vei-Han Chan ,  Ching-Hwa Chen

Inventor： Chuck Jang ,  Zhong Dong ,  Vei-Han Chan ,  Ching-Hwa Chen

IPC: H01L21/8238

CPC classification number: H01L21/02164 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/28211 ,  H01L21/28273 ,  H01L21/3162 ,  H01L21/31683 ,  H01L29/511

Abstract: Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer lifetime of the memory cells fabricated according to this invention.

Abstract translation: 通过原子层沉积沉积氧化铝以形成用于非易失性存储器件的多晶硅介电层的高k电介质。 增加的电容耦合可以允许在浮动栅极和控制栅极之间使用较厚的氧化物层，从而提高根据本发明制造的存储器单元的可靠性和更长寿命。

公开(公告)号：US06891221B2

公开(公告)日：2005-05-10

申请号：US10790578

申请日：2004-03-01

Applicant: Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

Inventor： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

IPC: G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  G11C16/0491 ,  H01L27/115

Abstract: In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. the cells are erased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

Abstract translation: 在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。 单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。 位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。 由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。 使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。 通过使用Fowler-Nordheim从浮置栅极到控制栅极的隧道，通过在浮栅的壁上形成的多晶硅氧化物来消除电池。

公开(公告)号：US06717846B1

公开(公告)日：2004-04-06

申请号：US09696085

申请日：2000-10-26

Applicant: Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

Inventor： Peter W. Lee ,  Hung-Sheng Chen ,  Vei-Han Chan

IPC: G11C1616

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  G11C16/0491 ,  H01L27/115

Abstract: In this invention a process for a flash memory cell and an architecture for using the flash memory cell is disclosed to provide a nonvolatile memory having a high storage density. Adjacent columns of cells share the same source and the source line connecting these sources runs vertically in the memory layout, connecting to the sources of adjacent columns memory cells. Bit lines connect to drains of cells in adjacent columns and are laid out vertically, alternating with source lines in an every other column scheme. Wordlines made of a second layer of polysilicon form control gates of the flash memory cells and are continuous over the full width of a memory partition. Programming is done in a vertical page using hot electrons to inject charge onto the floating gates. The cells are crased using Fowler-Nordheim tunneling of electrons from the floating gate to the control gate by way of inter polysilicon oxide formed on the walls of the floating gates.

Abstract translation: 在本发明中，公开了一种用于闪存单元的方法和用于使用闪存单元的架构，以提供具有高存储密度的非易失性存储器。 单元格的相邻列共享相同的源，并且连接这些源的源行在存储器布局中垂直运行，连接到相邻列存储单元的源。 位线连接到相邻列中的单元格的漏极，并且在每个其他列方案中垂直布置，与源极线交替。 由第二层多晶硅制成的字线形成闪存单元的控制栅极，并且在存储器分区的整个宽度上是连续的。 使用热电子在垂直页面中进行编程，以将电荷注入到浮动栅极上。 使用Fowler-Nordheim，通过在浮栅的壁上形成的多晶硅氧化物，利用Fowler-Nordheim将浮动栅极的电子隧穿到控制栅极进行电池堆积。

公开(公告)号：US06410956B1

公开(公告)日：2002-06-25

申请号：US09478864

申请日：2000-01-07

Applicant: Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

Inventor： Vei-Han Chan ,  Scott D. Luning ,  Mark Randolph ,  Nicholas H. Tripsas ,  Daniel Sobek ,  Janet Wang ,  Timothy J. Thurgate ,  Sameer Haddad

IPC: H01L2976

CPC classification number: H01L29/66825

Abstract: A system and method for providing a memory cell on a semiconductor is disclosed. In one aspect, the method and system include providing at least one gate stack on the semiconductor, depositing at least one spacer, and providing at least one source implant in the semiconductor. The at least one gate stack has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate stack. In another aspect, the method and system include providing at least one gate stack on the semiconductor, providing a first junction implant in the semiconductor, depositing at least one spacer, and providing a second junction implant in the semiconductor after the at least one spacer is deposited. The at least one gate stack has an edge. A portion of the at least one spacer is disposed at the edge of the at least one gate stack. In a third aspect, the method and system include providing at least one gate stack on the semiconductor, providing at least one source implant in the semiconductor, depositing at least one spacer after the at least one source implant is provided, and providing at least one drain implant in the semiconductor after the spacer is deposited. The at least one gate has an edge. A portion of the at least one spacer is disposed along the edge of the at least one gate.

Abstract translation: 公开了一种在半导体上提供存储单元的系统和方法。 在一个方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，沉积至少一个间隔物，以及在半导体中提供至少一个源极注入。 至少一个栅极堆叠具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极叠层的边缘设置。 在另一方面，该方法和系统包括在半导体上提供至少一个栅极叠层，在半导体中提供第一结注入，沉积至少一个间隔物，以及在至少一个间隔物之后在半导体中提供第二结注入 存放 至少一个栅极堆叠具有边缘。 所述至少一个间隔件的一部分设置在所述至少一个栅极叠层的边缘处。 在第三方面，所述方法和系统包括在半导体上提供至少一个栅极堆叠，在半导体中提供至少一个源极注入，在提供至少一个源极植入之后沉积至少一个间隔物，并且提供至少一个 在间隔物沉积之后在半导体中的漏极注入。 至少一个门具有边缘。 所述至少一个间隔物的一部分沿着所述至少一个栅极的边缘设置。

公开(公告)号：US6001713A

公开(公告)日：1999-12-14

申请号：US154074

申请日：1998-09-16

Applicant: Mark T. Ramsbey ,  Vei-Han Chan ,  Sameer Haddad ,  Chi Chang ,  Yu Sun ,  Raymond Yu

Inventor： Mark T. Ramsbey ,  Vei-Han Chan ,  Sameer Haddad ,  Chi Chang ,  Yu Sun ,  Raymond Yu

IPC: H01L21/28 ,  H01L21/265

CPC classification number: H01L21/28273

Abstract: Methods are provided for significantly reducing electron trapping in semiconductor devices having a floating gate and an overlying dielectric layer. The methods form a nitrogen-rich region within the floating gate near the interface to an overlying dielectric layer. The methods include selectively introducing nitrogen into the floating gate prior to forming the overlying dielectric layer. This forms an initial nitrogen concentration profile within the floating gate. An initial portion of the overlying dielectric layer is then formed of a high temperature oxide (HTO). The temperature within the floating gate is purposely raised to an adequately high temperature to cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards the interface with the overlying dielectric layer and an interface with an underlying layer. Consequently, the floating gate is left with a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The first nitrogen-rich region has been found to reduce electron trapping within the floating gate, which could lead to false programming of the floating gate. Unlike a conventional thermally grown oxide film, the high temperature oxide film within the interpoly dielectric layer advantageously prevents the surface of the floating gate from becoming too granular. As such, the resulting interpoly dielectric layer, which typically includes several films, can be formed more evenly.

Abstract translation: 提供了用于显着减少具有浮置栅极和上覆电介质层的半导体器件中的电子俘获的方法。 该方法在与上覆电介质层的界面附近的浮栅内形成富氮区。 所述方法包括在形成上覆电介质层之前将氮气选择性地引入浮栅。 这在浮动栅极内形成初始氮浓度分布。 然后由上覆电介质层的初始部分由高温氧化物（HTO）形成。 浮置栅极内的温度有意地升高到足够高的温度，以使得初始氮浓度分布由于大部分氮向与上覆介质层的界面的迁移以及与下层的界面而改变。 因此，浮置栅极在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域留下。 已经发现第一个富氮区域减少了浮动栅极内的电子俘获，这可能导致浮动栅极的错误编程。 与传统的热生长氧化膜不同，多聚电介质层内的高温氧化膜有利地防止浮栅的表面变得太细。 因此，可以更均匀地形成通常包括几个膜的所得到的互间介电层。

公开(公告)号：US5940709A

公开(公告)日：1999-08-17

申请号：US993599

申请日：1997-12-18

Applicant: Vei-Han Chan

Inventor： Vei-Han Chan

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8247 ,  H01L21/266

CPC classification number: H01L29/66825 ,  H01L21/2652

Abstract: A system and method for providing a memory in a semiconductor is disclosed. In one aspect, the method and system include providing a source implant in the semiconductor, providing a first anneal of the source implant in an oxidizing agent, and providing a drain implant in the semiconductor after the first anneal. In another aspect, the method and system include providing a source implant and a drain implant in the semiconductor, providing a mask, and providing an anneal of the source implant, the drain implant, and the mask in an oxidizing agent. The mask exposes the source implant while limiting exposure of at least a portion of the drain implant.

Abstract translation: 公开了一种在半导体中提供存储器的系统和方法。 在一个方面，该方法和系统包括在半导体中提供源注入，提供源植入物在氧化剂中的第一退火，以及在第一退火之后在半导体中提供漏极注入。 在另一方面，该方法和系统包括在半导体中提供源注入和漏极注入，提供掩模，并在氧化剂中提供源极注入，漏极注入和掩模的退火。 掩模暴露源植入物，同时限制漏极植入物的至少一部分的暴露。