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公开(公告)号：US20170249081A1
公开(公告)日：2017-08-31
申请号：US15088596
申请日：2016-04-01
发明人： Yiftach Tzori
IPC分类号： G06F3/06
CPC分类号： G06F13/24 , G06F3/061 , G06F3/0659 , G06F3/0688 , H04M1/72583
摘要： Systems and methods for decoupling host commands in a non-volatile memory system are disclosed. In one implementation, a non-volatile memory system includes a non-volatile memory and a controller in communication with the non-volatile memory. The controller is configured to translate a first command that is formatted according to a communication protocol to a second command that is formatted generically, store the first command in an expected queue, and store the second command in the expected queue with a command priority. The controller is further configured to execute the second command based on the command priority, translate a result of the executed second command into a format according to the communication protocol, and transmit the result of the executed second command in the format according to the communication protocol to a host system dependent upon a position of the first command in the expected queue.
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公开(公告)号：US20170213817A1
公开(公告)日：2017-07-27
申请号：US15087004
申请日：2016-03-31
发明人： Shiv Harit Mathur , Anand Sharma , Lakhdar Iguelmamene , Richard Jk Hong , Rajeswara Rao Bandaru
CPC分类号： H01L27/0629 , H01L24/06 , H01L27/0203 , H01L27/0292 , H01L2224/04042 , H01L2224/05553 , H01L2924/00014 , H01L2924/14 , H01L2224/05599
摘要： An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.
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公开(公告)号：US20170200501A1
公开(公告)日：2017-07-13
申请号：US14994525
申请日：2016-01-13
发明人： Nian Niles Yang , Chris Avila
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3459
摘要： A non-volatile memory system includes a plurality of NAND strings (or other arrangements) that form a monolithic three dimensional memory structure, bit lines, word lines, and one or more control circuits. Multiple NAND strings of the plurality of NAND strings have different select gates connected to different select lines. The multiple NAND strings are connected to a common bit line. The multiple NAND strings are connected to a common word line via their respective different select gates. The one or more control circuits concurrently program multiple memory cells on the multiple NAND strings.
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公开(公告)号：US20170125117A1
公开(公告)日：2017-05-04
申请号：US14928853
申请日：2015-10-30
CPC分类号： G11C16/3459 , G11C11/5628 , G11C16/10 , G11C29/021 , G11C29/028 , G11C2029/0409 , G11C2029/1202
摘要： Techniques are provided to adaptively determine when to begin verify tests for a particular data state based on a programming progress of a set of memory cells. A count is made in a program-verify iteration of memory cells which pass a verify test of a state N. The count is used to determine a subsequent program-verify iteration in which to perform a verify test of a higher state as a function of an amount by which the count exceeds a threshold count. In another approach, an optimum verify scheme is implemented on a per-group basis for groups of adjacent memory cells at different heights in a 3D memory device. In another approach, an optimum verify scheme is implemented on a per-layer basis for sets of memory cells at a common height or word line layer in a 3D memory device.
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公开(公告)号：US20170117021A1
公开(公告)日：2017-04-27
申请号：US14919289
申请日：2015-10-21
CPC分类号： G11C7/1006 , G11C11/5628 , G11C11/5635 , G11C2211/5641
摘要： A device includes a memory including a first set of storage elements and a second set of storage elements. The device further includes circuitry coupled to the memory and configured to perform a data folding operation to fold second data from the second set of storage elements with respect to first data stored at the first set of storage elements. Each storage element of the first set of storage elements is designated to store at least three bits per storage element, and each storage element of the second set of storage elements is designated to store at least two bits per storage element.
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公开(公告)号：US20170103025A1
公开(公告)日：2017-04-13
申请号：US14877614
申请日：2015-10-07
发明人： David Meyer , Satish Vasudeva
CPC分类号： G06F12/1408 , G06F12/0246 , G06F21/79 , G06F2212/1052 , G06F2212/7207 , G06F2221/2143 , G09C1/00 , H04L9/0618 , H04L9/0891 , H04L9/0894 , H04L2209/12 , H04L2209/24
摘要： In one embodiment, a memory system stores data encrypted with a cipher key in a block of a page in non-volatile memory, reads the cipher key version number associated with the page, determines whether the cipher key version number associated with the page is different from a cipher key version number of the cipher key used to encrypt the data and, if it is, writes a data pattern encrypted with the cipher key into the other blocks of the page, and stores the cipher key version number of the cipher key used to encrypt the data in the storage space in the non-volatile memory. Other embodiments are provided.
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公开(公告)号：US20170102882A1
公开(公告)日：2017-04-13
申请号：US14880793
申请日：2015-10-12
IPC分类号： G06F3/06
CPC分类号： G06F3/065 , G06F3/061 , G06F3/0616 , G06F3/0679
摘要： A data storage device includes a memory (including a single level cell (SLC) memory portion and a multilevel cell (MLC) memory portion), a plurality of data latches, and routing circuitry coupled to the plurality of data latches. The routing circuitry is configured to cause write data, received from a controller, to be stored at a data latch of the plurality of data latches. The routing circuitry is further configured to cause the write data to be copied from the data latch to a particular portion of the memory based on receiving a program mode command after the write data is stored at the data latch, where the program mode command indicates the particular portion as one of the SLC memory portion or the MLC memory portion.
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公开(公告)号：US20170084345A1
公开(公告)日：2017-03-23
申请号：US14860224
申请日：2015-09-21
发明人： Nian Niles Yang , Jim Fitzpatrick , Yiwei Song
CPC分类号： G11C16/34 , G11C16/0483 , G11C16/08 , G11C16/14 , G11C16/26 , G11C16/3459 , G11C29/02 , G11C29/024
摘要： A non-volatile memory system includes a plurality of groups of connected non-volatile memory cells (e.g., charge trapping memory cells), a select line, and a plurality of select gates connected to the select line. Each select gate is connected at an end (e.g. source end or drain side) of one of the groups of memory cells. The system includes one or more control circuits that are configured to determine whether the select gates are abnormal. If a select gate is determined to be abnormal, then one of the memory cells connected to the select gate is converted to operate as a select gate. The system will then perform memory operations by operating the converted memory cell as a select gate.
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公开(公告)号：US20170075572A1
公开(公告)日：2017-03-16
申请号：US14851833
申请日：2015-09-11
CPC分类号： G06F3/061 , G06F3/0607 , G06F3/0659 , G06F3/0685 , G06F3/0688 , G06F13/1605 , G06F13/1642 , G06F13/18
摘要： A storage device with a memory may implement software queueing that can supplement hardware accelerated queueing mechanisms. A software queue supplementing a hardware queue can extend the size and allow pending operations to proceed even if the hardware queue is saturated. The use of software-based queues may extend processing capacity in a hardware-accelerated front-end storage device architecture. The software queue may process excess commands that cannot be handled by a hardware queue with a limited depth.
摘要翻译： 具有存储器的存储设备可以实现可以补充硬件加速排队机制的软件排队。 补充硬件队列的软件队列可以扩展大小，并且即使硬件队列饱和也允许挂起的操作继续进行。 使用基于软件的队列可以在硬件加速的前端存储设备架构中扩展处理能力。 软件队列可以处理不能被有限深度的硬件队列处理的多余命令。
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公开(公告)号：US20170062069A1
公开(公告)日：2017-03-02
申请号：US14842550
申请日：2015-09-01
发明人： Nian Niles Yang , Abhijeet Manohar
CPC分类号： G11C16/3445 , G06F11/1012 , G06F11/1068 , G06F11/1072 , G06F11/1076 , G06F12/0246 , G11C11/5628 , G11C11/5642 , G11C16/24 , G11C16/3454 , G11C16/349 , G11C16/3495 , G11C29/021 , G11C29/028 , G11C29/52 , G11C29/78 , G11C2029/0401
摘要： A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.
摘要翻译： 具有存储器的存储设备可以通过修改存储器块的编程状态来改善耐久性和编程速度。 例如，块可以是三位存储器块，但是验证电平和读取余量的动态重新分配可以导致块像两位存储块一样起作用。 存储器块可以被设计用于每个单元的一定数量的位（即状态数），并且编程基于该数量。 然而，除了根据存储器设计的每个单元的位数进行编程之外，单级单元（SLC）编程仍然是可能的。 多个SLC编程步骤可用于通过存储器控制器修改某些存储器单元的状态数。
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