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公开(公告)号:US12068749B2
公开(公告)日:2024-08-20
申请号:US18203810
申请日:2023-05-31
Applicant: Reach Power, Inc.
Inventor: Asmita Dani , Christopher Joseph Davlantes
CPC classification number: H03K3/012 , H02M7/217 , H03F3/19 , H03G3/3036 , H03F2200/451 , H03G2201/103 , H03G2201/307
Abstract: A bidirectional RF circuit, preferably including a plurality of terminals, a switch, a transistor, a coupler, and a feedback network. The circuit can optionally include a drain matching network, an input matching network, and/or one or more tuning inputs. In some variations, the circuit can optionally include one or more impedance networks, such as an impedance network used in place of the feedback network; in some such variations, the circuit may not include a coupler, switch, and/or input matching network. A method for circuit operation, preferably including operating in an amplifier mode, operating in a rectifier mode, and/or transitioning between operation modes.
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公开(公告)号:US12021495B2
公开(公告)日:2024-06-25
申请号:US17566334
申请日:2021-12-30
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor: Junhyung Lee , Johannes Jacobus Emile Maria Hageraats , Yan Yan , Bumkyum Kim , Aravind Kumar Padyana , Joshua Haeseok Cho , Rimal Deep Singh , Bipul Agarwal
CPC classification number: H03G3/3036 , H03F3/19 , H04B1/40 , H03F2200/451 , H03G2201/103 , H03G2201/307
Abstract: Disclosed herein are signal amplifiers that include a plurality of switchable amplifier architectures so that particular gain modes can use dedicated amplifier architectures to provide desired characteristics for those gain modes, such as low noise figure or high linearity. The disclosed signal amplifier architectures provide tailored impedances using a degeneration block or matrix without using switches in the degeneration switching block. The disclosed signal amplifier architectures provide a plurality of gain modes where different gain modes use different paths through the amplifier architecture. Switches that are used to select the path through the amplifier architecture also provide targeted impedances in a degeneration block or matrix. The switches that select the gain path are provided in the amplifier architecture and are thus not needed or used in the degeneration block, thereby reducing the size of the package for the amplifier architecture.
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公开(公告)号:US11784735B2
公开(公告)日:2023-10-10
申请号:US17719300
申请日:2022-04-12
Applicant: Wilson Electronics, LLC
Inventor: Joshua Kent Barnes , Christopher Ken Ashworth
IPC: H04B7/14 , H04B17/40 , H04B17/327 , H04B17/336 , H03G3/30 , H04B7/15
CPC classification number: H04B17/40 , H03G3/3042 , H04B7/15 , H04B17/327 , H04B17/336 , H03G2201/103 , H03G2201/106 , H03G2201/307
Abstract: A technology is described for adjusting repeater gain based on user equipment need. A downlink path of the repeater can be deactivated. A deactivated throughput value can be received from the UE for data received at the UE in a selected time period. The downlink amplification path of the repeater can be activated. An activated throughput value for data received at the UE in the selected time period can be received from the UE. A difference can be determined between the deactivated throughput value and the activated throughput value. A repeater gain value can be reduced or bypassed when the deactivated throughput value is greater than the activated throughput value by a selected threshold value.
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公开(公告)号:US11784620B2
公开(公告)日:2023-10-10
申请号:US17592913
申请日:2022-02-04
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor: Xingyi Hua , Weiheng Chang
CPC classification number: H03G3/3042 , H03F3/245 , H04B1/44 , H03F2200/294 , H03F2200/451 , H03G2201/103 , H03G2201/307
Abstract: This disclosure relates to variable-gain amplifiers that include degeneration circuits configured to adapt to a gain mode that is currently being implemented. For example, a variable-gain amplifier can operate in a plurality of gain modes to amplify a signal with different levels of amplification. The variable-gain amplifier can include a gain circuit configured to amplify a signal and a degeneration circuit coupled to the gain circuit. The degeneration circuit can include an inductor and a switching-capacitive arm coupled in parallel to the inductor. The degeneration circuit can operate based on a current gain mode to change an inductance for the variable-gain amplifier.
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公开(公告)号:US11752356B2
公开(公告)日:2023-09-12
申请号:US16273519
申请日:2019-02-12
Applicant: NeuroEM Therapeutics, Inc.
Inventor: Gary W. Arendash , Rob Baranowski
CPC classification number: A61N1/40 , A61N1/0476 , A61N5/04 , H03G3/30 , H03G3/3036 , H03G3/3042 , H01Q1/273 , H03G2201/103 , H03G2201/106 , H03G2201/307
Abstract: In one example in accordance with the present disclosure, an antenna system is described. The antenna system includes an array of antennas. Each antenna emits electromagnetic waves and is presented with a load that is different from other antennas in the array. The antenna system also includes a control system. The control system includes a single transmitter to sequentially drive antenna sets, a switching device to select, for each activation period in an activation sequence, an antenna set to be driven, and a controller. The controller determines an actual power output of each antenna and generates an adjusted control signal for the single transmitter such that the output of each antenna is controlled to match a target power for that antenna, regardless of a load for the antenna.
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公开(公告)号:US20180331659A1
公开(公告)日:2018-11-15
申请号:US15969075
申请日:2018-05-02
Applicant: SKYWORKS SOLUTIONS, INC.
Inventor: Sabah Khesbak , Serge Francois Drogi
CPC classification number: H03F1/0255 , H03F1/0227 , H03F1/0233 , H03F1/0266 , H03F3/19 , H03F3/21 , H03F3/245 , H03F2200/102 , H03F2200/207 , H03F2200/336 , H03F2200/36 , H03F2200/387 , H03F2200/411 , H03F2200/417 , H03F2200/432 , H03F2200/451 , H03F2200/471 , H03F2203/7215 , H03F2203/7221 , H03G3/3042 , H03G2201/307 , H04B1/0475 , H04B2001/0408
Abstract: Envelope trackers providing compensation for power amplifier output load variation are provided herein. In certain configurations, a radio frequency (RF) system includes a power amplifier that amplifies an RF signal, an output detector coupled to an output of the power amplifier and that generates an output detection signal, an input detector coupled to an input of the power amplifier and that generates an input detection signal, and an envelope tracker that generates a power amplifier supply voltage for the power amplifier based on an envelope of the RF signal. The envelope tracker compensates the power amplifier for output load variation based on the output detection signal and the input detection signal.
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公开(公告)号:US20180287647A1
公开(公告)日:2018-10-04
申请号:US15924717
申请日:2018-03-19
Applicant: Panasonic Corporation
Inventor: YOHEI MORISHITA , TAKENORI SAKAMOTO
CPC classification number: H04B1/16 , H03G3/3042 , H03G3/3052 , H03G3/3078 , H03G2201/302 , H03G2201/307 , H04B1/0028
Abstract: A gain controller sets a gain code indicating an optimum gain, a cutoff frequency code indicating a cutoff frequency, and a number of bits code indicating a number of bits. An AEQ/VGA gain controller sets a frequency characteristic code indicating a frequency characteristic, a gain code indicating a gain after correction, and a number of bits code indicating a number of bits. An AEQ/VGA amplifies a baseband received signal on the basis of a gain code and corrects a frequency characteristic of the baseband received signal on the basis of a frequency characteristic code. An HPF cuts off a band below a cutoff frequency of an output signal from the AEQ/VGA on the basis of a cutoff frequency code. An ADC quantizes an output signal from the HPF using a number of bits based on a number of bits code and generates a digital received signal.
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公开(公告)号:US20180175807A1
公开(公告)日:2018-06-21
申请号:US15895863
申请日:2018-02-13
Applicant: pSemi Corporation
Inventor: Hossein Noori , Chih-Chieh Cheng
CPC classification number: H03F1/3205 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/18 , H03F2200/21 , H03F2200/211 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/24 , H03F2200/243 , H03F2200/249 , H03F2200/27 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/312 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/417 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/495 , H03F2200/546 , H03F2200/72 , H03F2200/75 , H03G1/0029 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G3/008 , H03G3/10 , H03G2201/106 , H03G2201/307 , H03G2201/504
Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
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公开(公告)号:US09929701B1
公开(公告)日:2018-03-27
申请号:US15272103
申请日:2016-09-21
Applicant: Peregrine Semiconductor Corporation
Inventor: Hossein Noori , Chih-Chieh Cheng
CPC classification number: H03F1/3205 , H03F1/56 , H03F3/195 , H03F3/72 , H03F2200/18 , H03F2200/21 , H03F2200/211 , H03F2200/213 , H03F2200/222 , H03F2200/225 , H03F2200/24 , H03F2200/243 , H03F2200/249 , H03F2200/27 , H03F2200/294 , H03F2200/297 , H03F2200/301 , H03F2200/306 , H03F2200/312 , H03F2200/387 , H03F2200/391 , H03F2200/399 , H03F2200/417 , H03F2200/451 , H03F2200/48 , H03F2200/489 , H03F2200/492 , H03F2200/495 , H03F2200/546 , H03F2200/72 , H03F2200/75 , H03G1/0029 , H03G1/0088 , H03G1/0094 , H03G3/001 , H03G3/008 , H03G3/10 , H03G2201/106 , H03G2201/307 , H03G2201/504
Abstract: A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” input stage and a “common gate” output stage can be turned on or off using the gate of the output stage. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input stage of each cascode. Further switches used for switching degeneration inductors, gate/sources caps and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
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公开(公告)号:US20090066414A1
公开(公告)日:2009-03-12
申请号:US12073686
申请日:2008-03-07
Applicant: Leonard Dauphinee , Lawrence M. Burns
Inventor: Leonard Dauphinee , Lawrence M. Burns
IPC: H03G3/20
CPC classification number: H01L22/20 , G01R31/2607 , G01R31/30 , G01R31/31723 , H01L2924/0002 , H03F3/211 , H03G3/3036 , H03G3/3052 , H03G2201/307 , H04N5/4446 , H04N5/52 , H04N7/102 , H01L2924/00
Abstract: A Variable Gain Amplifier (VGA) amplifies an input signal according to a gain, to produce an amplified signal. A detector module detects a power indicative of a power of the amplified signal. A comparator module compares the detected power to a high threshold, a low threshold and a target threshold intermediate the high and low thresholds. A controller module changes the gain of the VGA so as to drive the detected power in a direction toward the middle threshold when the comparator module indicates the detected power is not between the high and low thresholds.
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