公开(公告)号：US09143140B2

公开(公告)日：2015-09-22

申请号：US13370784

申请日：2012-02-10

申请人： David Lin ,  Suresh Balasubramanian

发明人： David Lin ,  Suresh Balasubramanian

IPC分类号： H03L7/06 ,  H03L7/081 ,  H03K5/135

CPC分类号： H03L7/0816 ,  H03K5/135 ,  H03K5/14 ,  H03L7/08

摘要： A delay circuit provides a quadrature-delayed strobe, a tightly controlled quadrature DLL and write/read leveling delay lines by using the same physical delay line pair. By multiplexing different usage models, the need for multiple delay lines is significantly reduced to only two delay lines per byte. As a result, the delay circuit provides substantial saving in terms of layout area and power.

摘要翻译： 延迟电路通过使用相同的物理延迟线对来提供正交延迟的选通脉冲，严格控制的正交DLL和写/读电平延迟线。 通过复用不同的使用模型，对多个延迟线的需求显着减少到每个字节仅两个延迟线。 因此，延迟电路在布局面积和功率方面提供了显着的节省。

公开(公告)号：US09054713B2

公开(公告)日：2015-06-09

申请号：US13959119

申请日：2013-08-05

申请人： ELPIDA MEMORY, INC.

发明人： Katsuhiro Kitagawa ,  Hiroki Takahashi

IPC分类号： H03L7/00 ,  H03L7/08 ,  H03L7/081 ,  H03L7/22 ,  G11C7/22 ,  G11C11/4076 ,  G11C29/12 ,  G11C29/14

CPC分类号： H03L7/0802 ,  G11C7/222 ,  G11C11/4076 ,  G11C29/12015 ,  G11C29/14 ,  H03L7/0816 ,  H03L7/22

摘要： Disclosed herein is a device that includes: a plurality of delay circuits each including an input node, an output node, a first power node and a second power node, and a control circuit. The delay circuits are coupled in series with the input node of a leading delay circuit receiving a first clock signal and the output node of a last delay circuit producing a second clock signal. The control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines. The first power nodes of the delay circuits are connected in common to the first power line, and the second power nodes the delay circuits are connected in common to the second power line.

摘要翻译： 这里公开了一种装置，其包括：多个延迟电路，每个延迟电路包括输入节点，输出节点，第一功率节点和第二功率节点，以及控制电路。 延迟电路与接收第一时钟信号的前导延迟电路的输入节点和最后一个延迟电路的输出节点串联耦合，产生第二时钟信号。 控制电路被耦合以接收第一和第二时钟信号，以控制在第一和第二电力线之间提供的工作电压。 延迟电路的第一功率节点共同连接到第一电力线，并且第二电力节点延迟电路共同连接到第二电力线。

公开(公告)号：US20150015310A1

公开(公告)日：2015-01-15

申请号：US14040829

申请日：2013-09-30

申请人： SK HYNIX INC.

发明人： Young Suk SEO

IPC分类号： H03K5/159 ,  H03L7/06

CPC分类号： H03L7/085 ,  H03L7/06 ,  H03L7/0812 ,  H03L7/0816

摘要： Provided is a clock delay detecting circuit and semiconductor apparatus using the same that is capable of generating a period signal whose period is a delay time of a clock, dividing the period signal, and counting the divided period signal. The clock delay detection circuit comprises a period signal generating unit configured to generate a counting control signal, a period signal dividing unit configured to generate a counting enable signal by dividing the counting control signal, and a counting unit configured to generate a delay information signal by counting the counting enable signal with a clock, wherein the counting control signal has a period with a predetermined time.

公开(公告)号：US08890593B1

公开(公告)日：2014-11-18

申请号：US14206409

申请日：2014-03-12

申请人： MagnaChip Semiconductor, Ltd.

发明人： Jung Hyun Kim ,  Brian Chung ,  Steve Kang

IPC分类号： H03L7/06 ,  H03L7/08

CPC分类号： H03L7/0816 ,  H03L7/0802

摘要： A delay-locked loop (DLL) operation mode control circuit and corresponding method are provided in which one of the output values from a display driver IC (DDI) is detected to switch a DLL block to standby mode. In examples, a CLKP/N frequency and CLKP/N common terminal voltage status are used to switch mode. Accordingly, since inoperable frequency domains otherwise present in a normal mode interval of the DLL block is included into standby mode, more stable operation of the DLL circuit is provided.

摘要翻译： 提供了延迟锁定环（DLL）操作模式控制电路和相应的方法，其中检测来自显示驱动器IC（DDI）的输出值之一以将DLL块切换到待机模式。 在示例中，使用CLKP / N频率和CLKP / N公共端电压状态来切换模式。 因此，由于在DLL模块的正常模式间隔中存在的不可操作的频域被包括在待机模式中，因此提供了DLL电路的更稳定的操作。

公开(公告)号：US20140333359A1

公开(公告)日：2014-11-13

申请号：US14338087

申请日：2014-07-22

申请人： Micron Technology, Inc.

发明人： Yantao Ma

IPC分类号： H03L7/08

CPC分类号： H03L7/08 ,  G11C7/04 ,  G11C7/222 ,  H03H11/26 ,  H03K5/133 ,  H03K2005/00058 ,  H03L7/0814 ,  H03L7/0816

摘要： Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a delay length, and, in a second mode, to determine an initial delay. The apparatus further including a delay line circuit coupled to the controller and includes delay elements. Each of the delay elements includes delay gates that are the same type of delay gate. The delay line circuit is configured to, in the first mode propagate a signal through one or more of the delay elements to provide a delayed signal. The delay line circuit is further configured to, in the second mode, propagate a pulse signal through one or more of the delay elements and provide a corresponding output signal from each of the one or more delay elements responsive to the pulse signal reaching an output of the corresponding delay element.

摘要翻译： 描述了使用延迟线延迟信号的装置和方法。 示例性装置包括控制器，被配置为处于第一模式，设置延迟长度，并且在第二模式中，确定初始延迟。 该装置还包括耦合到控制器并包括延迟元件的延迟线电路。 每个延迟元件包括相同类型的延迟门的延迟门。 延迟线电路被配置为在第一模式中通过一个或多个延迟元件传播信号以提供延迟信号。 延迟线电路还被配置为在第二模式中，通过一个或多个延迟元件传播脉冲信号，并且响应于脉冲信号提供来自一个或多个延迟元件中的每个延迟元件的相应输出信号， 相应的延迟元件。

公开(公告)号：US20140313847A1

公开(公告)日：2014-10-23

申请号：US14250460

申请日：2014-04-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： SEONG-HWAN JEONG ,  YANG-KI KIM ,  SEOK-HUN HYUN ,  JUNG-HWAN CHOI

IPC分类号： H03L7/08 ,  G11C8/18

CPC分类号： G11C8/18 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/095 ,  H03L7/10

摘要： A clock synchronization circuit includes a delay-locked loop (DLL) and a delay-locked control unit. The DLL is configured to generate an output clock signal by delaying an input clock signal by a delay time, and to execute a delay-locking operation in which the delay time is adjusted to a locked state according to a comparison between the output clock signal and the input clock signal. The delay-locked control unit configured to detect the locked state of the DLL, and to control the DLL based on the determined locked state

摘要翻译： 时钟同步电路包括延迟锁定环（DLL）和延迟锁定控制单元。 DLL被配置为通过将输入时钟信号延迟延迟时间来产生输出时钟信号，并且执行延迟锁定操作，其中延迟时间根据输出时钟信号和 输入时钟信号。 所述延迟锁定控制单元被配置为检测所述DLL的锁定状态，并且基于所确定的锁定状态来控制所述DLL

公开(公告)号：US20140286111A1

公开(公告)日：2014-09-25

申请号：US14294254

申请日：2014-06-03

申请人： SK hynix Inc.

发明人： Jong Ho JUNG

IPC分类号： G11C7/22

CPC分类号： G11C7/222 ,  G11C7/1066 ,  G11C7/22 ,  G11C2207/2272 ,  H03L7/0805 ,  H03L7/0816

摘要： A domain crossing circuit of a semiconductor apparatus includes a delay-locked loop block configured to generate a delay-locked loop clock signal in response to a clock signal and a clock enable signal; a clock enable block configured to generate the clock enable signal in response to the clock signal and a read command signal; and a command pass block configured to perform primary latency control according to the clock signal and secondary latency control according to the delay-locked loop clock signal, for the read command signal generated in response to a strobe signal, and generate a latency signal.

摘要翻译： 半导体装置的域交叉电路包括延迟锁定环路块，被配置为响应于时钟信号和时钟使能信号产生延迟锁定环路时钟信号; 时钟使能块，被配置为响应于所述时钟信号和读取命令信号而产生所述时钟使能信号; 以及命令传递块，被配置为根据所述延迟锁定环路时钟信号根据所述时钟信号和辅助等待时间控制对响应于选通信号而生成的所述读取命令信号执行主等待时间控制，并且生成等待时间信号。

公开(公告)号：US08841949B2

公开(公告)日：2014-09-23

申请号：US14102166

申请日：2013-12-10

申请人： Micron Technology, Inc.

发明人： Aaron Willey ,  Yantao Ma

IPC分类号： H03L7/06 ,  G11C7/22 ,  H03L7/08 ,  H03L7/081

CPC分类号： H03L7/0812 ,  G11C7/222 ,  H03K5/14 ,  H03L7/08 ,  H03L7/0816

摘要： Measurement initialization circuitry is described. Propagation of a start signal through a variable delay line may be stopped by either of two stop signals. One stop signal corresponds to a rising edge of a reference clock signal. A second stop signal corresponds to a falling edge of the reference clock signal. The start signal propagation is stopped responsive to the first to arrive of the first and second stop signals. Accordingly, in some examples, start signal propagation through a variable delay line may be stopped responsive to either a rising or falling edge of the reference clock signal.

摘要翻译： 描述了测量初始化电路。 通过可变延迟线传播起始信号可以通过两个停止信号中的任一个来停止。 一停信号对应于参考时钟信号的上升沿。 第二停止信号对应于参考时钟信号的下降沿。 响应于第一和第二停止信号的第一到达，起始信号传播停止。 因此，在一些示例中，响应于参考时钟信号的上升沿或下降沿可以停止通过可变延迟线的开始信号传播。

公开(公告)号：US08823431B2

公开(公告)日：2014-09-02

申请号：US13712625

申请日：2012-12-12

申请人： SK hynix Inc.

发明人： Jae Min Jang ,  Yong Ju Kim ,  Dae Han Kwon ,  Hae Rang Choi

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/093

摘要： A delay circuit includes a clock delay line, a command delay line, a delay line control block, and a shared shift register block. The clock delay line delays an input clock and generates a delayed clock. The command delay line delays a command signal and generates a delayed command signal. The delay line control block generates a control signal according to a result of comparing phases of a feedback clock which is generated as the delayed clock is delayed by a modeled delay value and the input clock. The shared shift register block sets delay amounts of the clock delay line and the command delay line to be substantially the same with each other, in response to the control signal.

摘要翻译： 延迟电路包括时钟延迟线，命令延迟线，延迟线控制块和共享移位寄存器块。 时钟延迟线延迟输入时钟并产生延迟时钟。 命令延迟线延迟命令信号并产生延迟命令信号。 延迟线控制块根据比较由延迟时钟延迟建模延迟值和输入时钟而产生的反馈时钟的相位的结果产生控制信号。 响应于控制信号，共享移位寄存器块将时钟延迟线和命令延迟线的延迟量设定为彼此基本相同。

公开(公告)号：US08786340B1

公开(公告)日：2014-07-22

申请号：US13869581

申请日：2013-04-24

申请人： Micron Technology, Inc.

发明人： Gideon Yong

IPC分类号： H03L7/06 ,  H03L7/08

CPC分类号： H03L7/0818 ,  G11C7/222 ,  H03L7/0814 ,  H03L7/0816

摘要： Apparatuses and methods for delaying signals using a delay circuit are described. An example apparatus includes a controller configured to set a delay length. The example apparatus further includes a delay circuit coupled to the controller. The delay circuit may include active delay stages of a plurality of delay stages that are configured to delay a first signal based on the delay length. Based on an increase to the delay length, the delay circuit is further configured to activate another delay stage of the plurality of delay stages responsive to a second signal that is based on the first signal.

摘要翻译： 描述了使用延迟电路来延迟信号的装置和方法。 一种示例性装置包括配置成设置延迟长度的控制器。 示例设备还包括耦合到控制器的延迟电路。 延迟电路可以包括被配置为基于延迟长度来延迟第一信号的多个延迟级的有效延迟级。 基于延迟长度的增加，延迟电路还被配置为响应于基于第一信号的第二信号来激活多个延迟级中的另一个延迟级。