公开(公告)号：US10210019B2

公开(公告)日：2019-02-19

申请号：US15145008

申请日：2016-05-03

申请人： International Business Machines Corporation

发明人： Fadi Y. Busaba ,  Harold W. Cain, III ,  Dan F. Greiner ,  Michael Karl Gschwind ,  Maged M. Michael ,  Valentina Salapura ,  Chung-Lung K. Shum ,  Timothy J. Slegel

IPC分类号： G06F3/06 ,  G06F9/46 ,  G06F13/24 ,  G06F9/26 ,  G06F9/52 ,  G06F9/48 ,  G06F9/50 ,  G06F9/54 ,  G06F13/38

摘要： When executed, a transaction-hint instruction specifies a transaction-count-to-completion (CTC) value for a transaction. The CTC value indicates how far a transaction is from completion. The CTC may be a number of instructions to completion or an amount of time to completion. The CTC value is adjusted as the transaction progresses. When a disruptive event associated with inducing transactional aborts, such as an interrupt or a conflicting memory access, is identified while processing the transaction, processing of the disruptive event is deferred if the adjusted CTC value satisfies deferral criteria. If the adjusted CTC value does not satisfy deferral criteria, the transaction is aborted and the disruptive event is processed.

公开(公告)号：US10198263B2

公开(公告)日：2019-02-05

申请号：US15060413

申请日：2016-03-03

申请人： Microsoft Technology Licensing, LLC

发明人： Douglas C. Burger ,  Aaron L. Smith

IPC分类号： G06F9/312 ,  G06F9/44 ,  G06F9/30 ,  G06F9/38 ,  G06F15/80 ,  G06F9/32 ,  G06F9/26 ,  G06F11/36 ,  G06F12/0862 ,  G06F9/35 ,  G06F12/1009 ,  G06F13/42 ,  G06F12/0806 ,  G06F15/78 ,  G06F9/46 ,  G06F9/52 ,  G06F9/345 ,  G06F9/355 ,  G06F12/0875 ,  G06F12/0811

摘要： Apparatus and methods are disclosed for nullifying one or more registers identified in a target field of a nullification instruction. In some examples of the disclosed technology, an apparatus can include memory and one or more block-based processor cores configured to fetch and execute a plurality of instruction blocks. One of the cores can include a control unit configured, based at least in part on receiving a nullification instruction, to obtain a register identification of at least one of a plurality of registers, based on a target field of the nullification instruction. A write to the at least one register associated with the register identification is nullified. The nullification instruction is in a first instruction block of the plurality of instruction blocks. Based on the nullified write to the at least one register, a subsequent instruction is executed from a second, different instruction block.

公开(公告)号：US20180349177A1

公开(公告)日：2018-12-06

申请号：US15870770

申请日：2018-01-12

申请人： Apple Inc.

发明人： Constantin Pistol ,  Daniel A. Chimene ,  Jeremy C. Andrus ,  Russell A. Blaine ,  Kushal Dalmia

IPC分类号： G06F9/48 ,  G06F9/38 ,  G06F9/26 ,  G06F9/50 ,  G06F9/30

摘要： Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US20180349175A1

公开(公告)日：2018-12-06

申请号：US15870760

申请日：2018-01-12

申请人： Apple Inc.

发明人： Jeremy C. Andrus ,  John G. Dorsey ,  James M. Magee ,  Daniel A. Chimene ,  Cyril de la Cropte de Chanterac ,  Bryan R. Hinch ,  Aditya Venkataraman ,  Andrei Dorofeev ,  Nigel R. Gamble ,  Russell A. Blaine ,  Constantin Pistol ,  James S. Ismail

IPC分类号： G06F9/48 ,  G06F9/38 ,  G06F9/26 ,  G06F9/50 ,  G06F9/30

摘要： Systems and methods are disclosed for scheduling threads on a processor that has at least two different core types, such as an asymmetric multiprocessing system. Each core type can run at a plurality of selectable voltage and frequency scaling (DVFS) states. Threads from a plurality of processes can be grouped into thread groups. Execution metrics are accumulated for threads of a thread group and fed into a plurality of tunable controllers for the thread group. A closed loop performance control (CLPC) system determines a control effort for the thread group and maps the control effort to a recommended core type and DVFS state. A closed loop thermal and power management system can limit the control effort determined by the CLPC for a thread group, and limit the power, core type, and DVFS states for the system. Deferred interrupts can be used to increase performance.

公开(公告)号：US09760511B2

公开(公告)日：2017-09-12

申请号：US14509533

申请日：2014-10-08

申请人： International Business Machines Corporation

发明人： Jonathan D. Bradbury ,  Fadi Y. Busaba ,  Mark S. Farrell ,  Charles W. Gainey, Jr. ,  Dan F. Greiner ,  Lisa C. Heller ,  Christian Jacobi ,  Jeffrey P. Kubala ,  Frank Lehnert ,  Bernd Nerz ,  Damian L. Osisek ,  Donald W. Schmidt ,  Timothy J. Slegel

IPC分类号： G06F12/00 ,  G06F13/24 ,  G06F13/00 ,  G06F9/26 ,  G06F13/26 ,  G06F9/455 ,  G06F9/46

CPC分类号： G06F13/26 ,  G06F9/45558 ,  G06F9/46 ,  G06F2009/45579

摘要： A system and method of implementing a modified priority routing of an input/output (I/O) interruption. The system and method determines whether the I/O interruption is pending for a core and whether any of a plurality of guest threads of the core is enabled for guest thread processing of the interruption in accordance with the determining that the I/O interruption is pending. Further, the system and method determines whether at least one of the plurality of guest threads enabled for guest thread processing is in a wait state and, in accordance with the determining that the at least one of the plurality of guest threads enabled for guest thread processing is in the wait state, routes the I/O interruption to a guest thread enabled for guest thread processing and in the wait state.

公开(公告)号：US09755947B2

公开(公告)日：2017-09-05

申请号：US13746104

申请日：2013-01-21

申请人： Intel Corporation

发明人： Robert J. Munoz

IPC分类号： H04L12/751 ,  G06F9/30 ,  G06F9/38 ,  G06F9/26 ,  H04L12/933 ,  H04L12/935 ,  H04L12/851 ,  H04L12/931

CPC分类号： H04L45/08 ,  G06F9/264 ,  G06F9/30058 ,  G06F9/30061 ,  G06F9/30094 ,  G06F9/3885 ,  H04L47/2441 ,  H04L47/2483 ,  H04L49/101 ,  H04L49/109 ,  H04L49/3009 ,  H04L49/351

摘要： Described embodiments process data packets received by a switch coupled to a network processor. The switch determines whether one or more rules for classifying and processing the received packet are stored in an internal classification database of the switch. If one or more rules are stored in the internal database, the switch updates statistics corresponding to each of the rules and classifies and processes the received packet in accordance with the rules. If no associated rules are stored in the internal database, the switch tags the received packet with metadata and forwards the packet to the network processor. The network processor determines one or more rules for classifying and processing the forwarded packet in a classification database of the network processor and updates statistics corresponding to each rule. The network processor classifies and processes the packet in accordance with the rules and updates the internal database of the switch.

公开(公告)号：US09710386B1

公开(公告)日：2017-07-18

申请号：US13961685

申请日：2013-08-07

申请人： Symantec Corporation

发明人： Xianbo Zhang ,  Gaurav Makin ,  Steve Vranyes ,  Sinh Nguyen ,  Smitha Cauligi

IPC分类号： G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F12/0862 ,  G06F9/50 ,  G06F9/48

CPC分类号： G06F12/0862 ,  G06F9/4856 ,  G06F9/5016 ,  G06F12/00 ,  G06F12/0868 ,  G06F2212/1016 ,  G06F2212/151 ,  G06F2212/313 ,  G06F2212/6024 ,  G06F2212/6026

摘要： A computer-implemented method for prefetching subsequent data segments may include (1) identifying a storage system that receives sequential read requests from a sequential-access computing job and random-access read requests from a random-access computing job, (2) observing a plurality of requests to read a plurality of data segments stored by the storage system, (3) determining that the plurality of data segments are stored contiguously by the storage system and that the plurality of requests originate from the sequential-access computing job, and (4) prefetching a subsequent data segment that is directly subsequent to the plurality of data segments in response to determining that the plurality of requests originate from the sequential-access computing job. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US09501395B2

公开(公告)日：2016-11-22

申请号：US15004462

申请日：2016-01-22

申请人： International Business Machines Corporation

发明人： Stuart E. Carney

IPC分类号： G06F12/00 ,  G06F9/26 ,  G06F9/34 ,  G06F12/02 ,  G06F9/45 ,  H03M7/30 ,  G06F9/30

CPC分类号： G06F12/023 ,  G06F8/4434 ,  G06F9/30178 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/3059 ,  H03M7/3068

摘要： Two-dimensional compressed data sets can be re-aligned while preserving compression of the data. A set of one or more shifts and a corresponding set of one or more first dimension indices into a two-dimensional compressed data set for re-aligning the two-dimensional compressed data set are determined. Impact of re-aligning upon each vector in the second dimension of the two-dimensional compressed data set is determined while the two-dimensional compressed data set remains compressed. New compressed vectors are created in the second dimension resulting from re-aligning. Compression information is modified for each of the original vectors of the two-dimensional compressed data set that remain after re-aligning based, at least in part, on the new compressed vectors. A re-aligned version of the two-dimensional compressed data set is created with the new compressed vectors, and the remaining original vectors with their modified compression information.

摘要翻译： 可以在保留压缩数据的同时重新对齐二维压缩数据集。 确定一组一个或多个位移和一组一个或多个第一维度索引到用于重新对准二维压缩数据集的二维压缩数据集中。 在二维压缩数据集保持压缩的同时确定对二维压缩数据集的第二维度中的每个向量进行重新对准的影响。 在重新对齐产生的第二维中创建新的压缩向量。 至少部分地基于新的压缩向量，对重新对准之后保留的二维压缩数据集的每个原始向量的压缩信息进行修改。 使用新的压缩向量创建二维压缩数据集的重新对齐版本，并且使用其修改的压缩信息创建剩余的原始向量。

公开(公告)号：US09477586B1

公开(公告)日：2016-10-25

申请号：US13288890

申请日：2011-11-03

申请人： Sam Hedinger ,  Philip Clarke

发明人： Sam Hedinger ,  Philip Clarke

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F9/26

CPC分类号： G06F12/00 ,  G06F1/3225 ,  G06F1/3275 ,  G06F11/34 ,  G06F13/16 ,  Y02D10/13 ,  Y02D10/14

摘要： Memory controller circuitry may process the memory access requests by reordering the sequence of requests. Reordering the sequence of requests may decrease the power consumption of the memory controller and system memory associated with the memory controller. The memory controller may operate in at least an unconstrained power mode, a priority mode, and a constrained power mode. In the unconstrained power mode, the memory controller may process memory access requests at elevated and power consumption levels. In the priority mode, the memory controller may process memory access requests from select sources with reduced power consumption. In the constrained power mode, the memory controller may process all memory access requests at reduced power consumption levels. Capacitive-model based power monitoring circuitry may be used to monitor the interactions between the memory controller and the system memory to dynamically adjust the operating mode of the memory controller.

摘要翻译： 存储器控制器电路可以通过重新排序请求序列来处理存储器访问请求。 重新排序请求序列可能会降低与存储器控制器相关联的存储器控​​制器和系统存储器的功耗。 存储器控制器可以以至少一个无约束功率模式，优先模式和受限功率模式运行。 在无约束电源模式下，存储器控制器可以在升高和功耗级别处理存储器访问请求。 在优先模式下，存储器控制器可以以降低的功耗处理来自选择源的存储器访问请求。 在受限制的功率模式中，存储器控制器可以以降低的功率消耗级别处理所有存储器访问请求。 基于电容模型的电力监控电路可用于监视存储器控制器和系统存储器之间的交互以动态地调整存储器控制器的操作模式。

公开(公告)号：US09459908B2

公开(公告)日：2016-10-04

申请号：US14696025

申请日：2015-04-24

申请人： International Business Machines Corporation

发明人： Manu A. Anand ,  Charles S. Graham ,  Timothy J. Schimke

IPC分类号： G06F9/455 ,  G06F9/46 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34 ,  G06F13/10

CPC分类号： G06F9/45558 ,  G06F13/102 ,  G06F13/4221 ,  G06F2009/45579 ,  G06F2009/45583

摘要： A method, system and computer program product are provided for implementing dynamic configuration of a Single Root Input/Output Virtualization (SRIOV) virtual function in a virtualized system. A management function, a hypervisor, a hypervisor based PF device driver and a partition based virtual function (VF) device driver are used to implement usage based VF resizing. The management function periodically queries the SRIOV adapter for activity statistics for every assigned virtual function. The management function builds a usage heuristic based on these statistics and calculates VF resource usage based on these statistics. The usage information determines whether VF resources need to be scaled-up or scaled-down. A corresponding resize event is generated and send by the management function to both the hypervisor based PF device driver and partition based VF device driver. Both the PF and VF device drivers scale to the corresponding VF resource of the resize event.