公开(公告)号：US11276573B2

公开(公告)日：2022-03-15

申请号：US16703248

申请日：2019-12-04

申请人： Applied Materials, Inc.

发明人： Bo Qi ,  Zeqing Shen ,  Abhijit Mallick

IPC分类号： H01L21/44 ,  H01L21/033 ,  C23C16/28 ,  C23C16/50

摘要： An exemplary method may include delivering a boron-containing precursor to a processing region of a semiconductor processing chamber. The method may also include forming a plasma within the processing region of the semiconductor processing chamber from the boron-containing precursor. The method may further include depositing a boron-containing material on a substrate disposed within the processing region of the semiconductor processing chamber. The boron-containing material may include greater than 50% of boron. In some embodiments, the boron-containing material may include substantially all boron. In some embodiments, the method may further include delivering at least one of a germanium-containing precursor, an oxygen-containing precursor, a silicon-containing precursor, a phosphorus-containing precursor, a carbon-containing precursor, and/or a nitrogen-containing precursor to the processing region of the semiconductor processing chamber. The boron-containing material may further include at least one of germanium, oxygen, silicon, phosphorus, carbon, and/or nitrogen.

公开(公告)号：US11264359B2

公开(公告)日：2022-03-01

申请号：US17028629

申请日：2020-09-22

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Kuei Hsu ,  Ming-Chih Yew ,  Shu-Shen Yeh ,  Che-Chia Yang ,  Po-Yao Lin ,  Shin-Puu Jeng

IPC分类号： H01L23/495 ,  H01L23/34 ,  H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H01L21/4763 ,  H01L25/065 ,  H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00

摘要： An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

公开(公告)号：US11257745B2

公开(公告)日：2022-02-22

申请号：US16641219

申请日：2017-09-29

申请人： INTEL CORPORATION

发明人： Aleksandar Aleksov ,  Veronica Strong ,  Kristof Darmawikarta ,  Arnab Sarkar

IPC分类号： H05K1/00 ,  H05K1/03 ,  H05K1/09 ,  H05K1/11 ,  H05K1/18 ,  H05K3/02 ,  H05K3/10 ,  H05K3/40 ,  H05K3/46 ,  H01L21/00 ,  H01L21/02 ,  H01L21/31 ,  H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L21/66 ,  H01L21/70 ,  H01L21/469 ,  H01L21/4763 ,  H01L21/8246 ,  H01L23/00 ,  H01L23/28 ,  H01L23/31 ,  H01L23/48 ,  H01L23/52 ,  H01L23/58 ,  H01L23/485 ,  H01L23/495 ,  H01L23/498 ,  H01L23/522 ,  G06K19/02 ,  G06K19/077 ,  H05K3/18

摘要： A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

公开(公告)号：US11239141B2

公开(公告)日：2022-02-01

申请号：US17031486

申请日：2020-09-24

申请人： INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

发明人： Ren-Shin Cheng ,  Shih-Hsien Wu ,  Yu-Wei Huang ,  Chih Ming Shen ,  Yi-Chieh Tsai

IPC分类号： H01L23/495 ,  H01L23/48 ,  H01L23/28 ,  H01L21/00 ,  H01L21/44 ,  H05K5/02 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

摘要： A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively.

公开(公告)号：US11233001B2

公开(公告)日：2022-01-25

申请号：US16712347

申请日：2019-12-12

申请人： SHINKO ELECTRIC INDUSTRIES CO., LTD.

发明人： Shota Miki ,  Naoki Kobayashi

IPC分类号： H01L23/34 ,  H01L23/48 ,  H01L23/28 ,  H01L21/00 ,  H01L21/44 ,  H05K1/00 ,  H05K1/14 ,  H05K7/00 ,  H01L23/498 ,  H01L23/00 ,  H01L23/522 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

摘要： An interconnect board includes: a first substrate; a second substrate having an outer shape smaller than an outer shape of the first substrate and mounted on the first substrate; and an adhesive layer bonding the first substrate and the second substrate together and having a fillet contacting a side surface of the second substrate. The fillet has a raised portion raised from a level of a top surface of the second substrate to a level higher than the top surface of the second substrate.

公开(公告)号：US11212914B2

公开(公告)日：2021-12-28

申请号：US16622108

申请日：2019-04-24

申请人： BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

发明人： Xingjun Shu ,  Jianwu Wu ,  Xi Chen ,  Xinda Li ,  Shengwei Yang ,  Yadong Zhang ,  Jianye Tang ,  Jiaqiang Wang

IPC分类号： H05K1/00 ,  H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/06 ,  H05K3/12 ,  H05K3/40 ,  H05K3/46 ,  H01L21/02 ,  H01L21/44 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L21/607 ,  H01L23/02 ,  H01L23/06 ,  H01L23/34 ,  H01L23/36 ,  H01L23/42 ,  H01L23/48 ,  H01L23/52 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538

摘要： The present disclosure provides a circuit board, including a substrate on which a first conductive layer and an electronic device are disposed, wherein the first conductive layer is disposed on a first surface of the substrate, and wherein a bottom end of the electronic device is disposed on the first conductive layer through the substrate. The present disclosure provides a display device.

公开(公告)号：US11205633B2

公开(公告)日：2021-12-21

申请号：US16736416

申请日：2020-01-07

申请人： Kulicke and Soffa Industries, Inc.

发明人： Adeel Ahmad Bajwa ,  Thomas J. Colosimo, Jr.

IPC分类号： H01L21/44 ,  H01L23/00

摘要： A bonding system for bonding a semiconductor element to a substrate is provided. The bonding system includes a substrate oxide reduction chamber configured to receive a substrate. The substrate includes a plurality of first electrically conductive structures. The substrate oxide reduction chamber is configured to receive a reducing gas to contact each of the plurality of first electrically conductive structures. The bonding system also includes a substrate oxide prevention chamber for receiving the substrate after the reducing gas contacts the plurality of first electrically conductive structures. The substrate oxide prevention chamber has an inert environment when receiving the substrate. The bonding system also includes a reducing gas delivery system for providing a reducing gas environment during bonding of a semiconductor element to the substrate.

公开(公告)号：US11195785B2

公开(公告)日：2021-12-07

申请号：US16891443

申请日：2020-06-03

申请人： Samsung Electronics Co., Ltd.

发明人： Yukyung Park ,  Seungkwan Ryu ,  Yunseok Choi

IPC分类号： H01L23/12 ,  H01L23/14 ,  H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H01L23/498 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48 ,  H01L23/532

摘要： An interposer includes a base layer having a first surface and a second surface, a redistribution structure on the first surface, an interposer protection layer on the second surface, a pad wiring layer on the interposer protection layer, an interposer through electrode passing through the base layer and the interposer protection layer and electrically connecting the redistribution structure to the pad wiring layer, an interposer connection terminal attached to the pad wiring layer, and a wiring protection layer including a first portion covering a portion of the interposer protection layer adjacent to the pad wiring layer, a second portion covering a portion of a top surface of the pad wiring layer, and a third portion covering a side surface of the pad wiring layer. The third portion is disposed between the first portion and the second portion. The first to third portions have thicknesses different from each other.

公开(公告)号：US11177225B2

公开(公告)日：2021-11-16

申请号：US16781196

申请日：2020-02-04

申请人： International Business Machines Corporation

发明人： Bahman Hekmatshoartabari ,  Takashi Ando ,  Alexander Reznicek ,  Nanbo Gong

IPC分类号： H01L21/44 ,  H01L23/52 ,  H01L23/00 ,  H01L21/02 ,  H01L21/768 ,  H01L49/02

摘要： Fabrication of a physically unclonable function containing semiconductor device by fabricating a first electrode of the semiconductor device, randomly nucleating material regions upon a surface of the first electrode and forming a second electrode upon the first electrode and at least a portion of the randomly nucleated regions.

公开(公告)号：US11158558B2

公开(公告)日：2021-10-26

申请号：US16464547

申请日：2016-12-29

申请人： INTEL CORPORATION

发明人： Rahul Jain ,  Kyu Oh Lee ,  Siddharth K. Alur ,  Wei-Lun K. Jen ,  Vipul V. Mehta ,  Ashish Dhall ,  Sri Chaitra J. Chavali ,  Rahul N. Manepalli ,  Amruthavalli P. Alur ,  Sai Vadlamani

IPC分类号： H01L23/48 ,  H01L21/00 ,  H01L21/44 ,  H05K7/00 ,  H01R9/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00 ,  H01L25/065 ,  H01L23/532 ,  H01L23/498

摘要： An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.