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公开(公告)号:US11239141B2
公开(公告)日:2022-02-01
申请号:US17031486
申请日:2020-09-24
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Ren-Shin Cheng , Shih-Hsien Wu , Yu-Wei Huang , Chih Ming Shen , Yi-Chieh Tsai
IPC: H01L23/495 , H01L23/48 , H01L23/28 , H01L21/00 , H01L21/44 , H05K5/02 , H01L23/498 , H01L21/56 , H01L23/31
Abstract: A lead frame package including first conductive layer, first electronic component, lead frames, second conductive layer and package body. First conductive layer has conductive carriers. First electronic component has first pins. Lead frames and first pins are respectively electrically connected to conductive carriers. Second conductive layer has conductive joints respectively electrically connected to lead frames so as to be electrically connected to at least a part of conductive carriers via lead frames. Package body encapsulates first conductive layer, first electronic component, and lead frames. First conductive layer and second conductive layer are located on two opposite sides of first electronic component, respectively.
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公开(公告)号:US09013892B2
公开(公告)日:2015-04-21
申请号:US13912207
申请日:2013-06-07
Applicant: Industrial Technology Research Institute
Inventor: Chang-Chih Liu , Hsun Yu , Peng-Shu Chen , Shih-Hsien Wu
IPC: H05K7/00 , H01L25/00 , H01L23/498 , H01L23/522
CPC classification number: H01L25/00 , H01L23/481 , H01L23/49822 , H01L23/49833 , H01L23/5223 , H01L23/5227 , H01L23/64 , H01L24/02 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L2224/02375 , H01L2224/0239 , H01L2224/0401 , H01L2224/05548 , H01L2224/13024 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/1703 , H01L2224/17106 , H01L2224/17515 , H01L2224/48091 , H01L2224/48101 , H01L2224/4813 , H01L2224/48137 , H01L2224/4917 , H01L2224/49175 , H01L2224/49177 , H01L2224/73204 , H01L2224/73257 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/3011 , H01L2924/01079 , H01L2924/01029 , H01L2924/01028 , H01L2924/01047 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
Abstract: A chip stacking structure including a plurality of microbump structures, a plurality of first substrates, at least one first space layer, a plurality of second substrates and at least one second space layer is provided. The first substrates are stacked upon each other by a portion of the microbump structures, and each of the first substrates includes at least one first redistribution layer. The first space layer is located between the stacked first substrates. The second substrates are stacked on at least one of the first substrates by another portion of the microbump structures, and each of the second substrates includes at least one second redistribution layer. The second space layer is located between the stacked first and second substrates. The first redistribution layers, the second redistribution layers and the microbump structures form a plurality of impedance elements, and the impedance elements provide a specific oscillation frequency.
Abstract translation: 提供了包括多个微型块结构,多个第一基板,至少一个第一空间层,多个第二基板和至少一个第二空间层的芯片堆叠结构。 第一基板通过微型块结构的一部分彼此堆叠,并且每个第一基板包括至少一个第一再分布层。 第一空间层位于堆叠的第一基板之间。 第二基板通过微型块结构的另一部分堆叠在至少一个第一基板上,并且每个第二基板包括至少一个第二再分布层。 第二空间层位于堆叠的第一和第二基板之间。 第一再分布层,第二再分配层和微型块结构形成多个阻抗元件,并且阻抗元件提供特定的振荡频率。
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公开(公告)号:US11061694B2
公开(公告)日:2021-07-13
申请号:US16677301
申请日:2019-11-07
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Chien-Min Hsu , Shih-Hsien Wu
Abstract: A reconfigurable data bus system comprises a driver, a receiver, a data bus and a detector. The driver stores an electrical parameter data base. The electrical parameter data base includes a plurality of different signal-to-ground ratios and a plurality of signal quality parameters corresponding to the signal-to-ground ratios. The data bus includes a plurality of signal lines electrically connected between the driver and the receiver. The detector is electrically connected to the data bus and the driver. The detector is configured to detect a current signal quality parameter of the data bus and transmit the current signal quality parameter to the driver. The driver is selectively reconfigured a current signal-to-ground ratio according to a current signal quality parameter of the data bus and the electrical parameter database.
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公开(公告)号:US10405418B2
公开(公告)日:2019-09-03
申请号:US15387604
申请日:2016-12-21
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Chien-Min Hsu , Shih-Hsien Wu
Abstract: A differential signal transmitting circuit board includes a substrate, at least two differential conductive elements, and at least one insulating element. The differential conductive elements are disposed in the substrate. The insulating element is disposed in the substrate. The insulating element is close to or contacted to the differential conductive elements. A material of the substrate has a first equivalent dielectric constant. A material of the insulating element has a second equivalent dielectric constant. The first equivalent dielectric constant is different from the second equivalent dielectric constant.
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公开(公告)号:US11955417B2
公开(公告)日:2024-04-09
申请号:US17550602
申请日:2021-12-14
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Tsung-Yi Hung , Shih-Hsien Wu
IPC: H01L23/498 , H01L23/00
CPC classification number: H01L23/49827 , H01L23/49816 , H01L23/49822 , H01L23/49838 , H01L24/16 , H01L2224/16227
Abstract: An electronic device includes a substrate, an upper conductive layer, and a lower conductive layer. The substrate has a plurality of inner vias and has an upper surface and a lower surface. The upper conductive layer includes an upper ground trace and an upper signal pad disposed on the upper surface. The upper ground trace is electrically connected to the ground vias and has an upper hollow portion exposing a part of the upper surface. The upper signal pad is disposed on the part of the upper surface exposed by the upper hollow portion and electrically connected to the signal via. The lower conductive layer includes a lower ground trace and a lower signal pad disposed on the lower surface. The lower conductive trace is electrically connected to the ground vias and has a lower hollow portion exposing a part of the lower surface. The lower signal pad is disposed on the part of the lower surface exposed by the lower hollow portion and electrically connected to the signal via.
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公开(公告)号:US20140048908A1
公开(公告)日:2014-02-20
申请号:US13797366
申请日:2013-03-12
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Peng-Shu Chen , Min-Lin Lee , Shih-Hsien Wu , Shur-Fen Liu
IPC: H01L23/48
CPC classification number: H01L23/48 , H01L21/02107 , H01L23/147 , H01L23/481 , H01L23/49827 , H01L23/5223 , H01L23/5228 , H01L23/64 , H01L23/66 , H01L25/0657 , H01L2224/0401 , H01L2224/05009 , H01L2224/06181 , H01L2224/13111 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16235 , H01L2224/81192 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor substrate assembly is proposed. The semiconductor interposer comprises a substrate having a first surface and a second surface opposite to the first surface, a first conductive pad, a second conductive pad and a conductive pillar. The first conductive pad is formed at a predetermined location of the first surface of the substrate. The second conductive pad is formed at a predetermined location of the second surface of the substrate as compared with the position of the first conductive pad. The conductive pillar is formed in the substrate and contacts with one of the first conductive pad and the second conductive pad.
Abstract translation: 提出了一种半导体衬底组件。 半导体插入器包括具有第一表面和与第一表面相对的第二表面的衬底,第一导电焊盘,第二导电焊盘和导电柱。 第一导电焊盘形成在基板的第一表面的预定位置处。 与第一导电焊盘的位置相比,第二导电焊盘形成在基板的第二表面的预定位置处。 导电柱形成在基板中并与第一导电焊盘和第二导电焊盘之一接触。
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公开(公告)号:US20240220694A1
公开(公告)日:2024-07-04
申请号:US18149158
申请日:2023-01-03
Applicant: Industrial Technology Research Institute
Inventor: Sheng-Che Hung , Shih-Hsien Wu , Hsu-Wei Liu , Tzong-Lin Wu
IPC: G06F30/39
CPC classification number: G06F30/39 , G06F2119/06
Abstract: A power design architecture including a power supply circuit, a power wiring, at least one chip, a power ring, and a first reference conductor is provided. The power wiring is connected to the power supply circuit. The power ring is disposed around the chip and electrically connected to the chip and the power wiring. The first reference conductor is electrically connected to the chip. Low self-impedance is maintained at any position of the power ring.
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公开(公告)号:US11756865B2
公开(公告)日:2023-09-12
申请号:US17141035
申请日:2021-01-04
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Sheng-Che Hung , Shih-Hsien Wu , Yu-Wei Huang
IPC: H01L23/485 , H05K1/11 , H05K3/30 , H05K3/42
CPC classification number: H01L23/485 , H05K1/114 , H05K1/115 , H05K3/303 , H05K3/421 , H05K2201/09609
Abstract: An electronic device having a substrate includes a substrate and at least one outer layer. The substrate has a plurality of first vias. The outer layer has a plurality of second vias. The outer layer is disposed on a side of the substrate. The first vias have a larger distribution density or quantity than the second vias so that a portion of the first vias are electrically connected to the second vias, and a portion of the first vias are electrically floating.
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公开(公告)号:US10448501B2
公开(公告)日:2019-10-15
申请号:US14968021
申请日:2015-12-14
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Shih-Hsien Wu
Abstract: A circuit structure includes an annular conductor, a conductive via and at least one extension conductor. The annular conductor extends along a direction. The conductive via is disposed in the annular conductor and extending along the direction. The at least one extension conductor is electrically connected to at least one end of the annular conductor and extending toward the conductive via.
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公开(公告)号:US10276908B2
公开(公告)日:2019-04-30
申请号:US15468796
申请日:2017-03-24
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor: Yu-Wei Huang , Shih-Hsien Wu , Wei-Chung Lo
IPC: H01P3/12
Abstract: An electromagnetic wave transmission board comprises a substrate. The substrate comprises a first dielectric layer and a second dielectric layer, and the first dielectric layer is stacked on the second dielectric layer. The first dielectric layer and the second dielectric layer together form a wave guiding space. The wave guiding space is configured for transmitting electromagnetic wave.
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