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    Embedding magnetic material, in a cored or coreless semiconductor package
    4.
    发明授权
    Embedding magnetic material, in a cored or coreless semiconductor package 有权

    公开(公告)号：US11355459B2

    公开(公告)日：2022-06-07

    申请号：US15982652

    申请日：2018-05-17

    申请人： Intel Corporation

    发明人： Kyu-Oh Lee ,  Sai Vadlamani ,  Rahul Jain ,  Junnan Zhao ,  Ji Yong Park ,  Cheng Xu ,  Seo Young Kim

    IPC分类号： H01L23/60 ,  H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F1/12 ,  H01F41/14

    摘要： Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure. The primer layer may comprise one or more of a build-up layer, a photoimageable dielectric layer, and a metal mask.

    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
    5.
    发明授权
    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate 有权

    公开(公告)号：US11139264B2

    公开(公告)日：2021-10-05

    申请号：US16586820

    申请日：2019-09-27

    申请人： Intel Corporation

    发明人： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

    IPC分类号： H01L23/00 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

    摘要： Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
    6.
    发明授权
    Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate 有权

    公开(公告)号：US10468374B2

    公开(公告)日：2019-11-05

    申请号：US15475175

    申请日：2017-03-31

    申请人： Intel Corporation

    发明人： Rahul Jain ,  Ji Yong Park ,  Kyu Oh Lee

    IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

    摘要： Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

    Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrate
    10.
    发明授权
    Methods to pattern TFC and incorporation in the ODI architecture and in any build up layer of organic substrate 有权

    公开(公告)号：US11581271B2

    公开(公告)日：2023-02-14

    申请号：US16353164

    申请日：2019-03-14

    申请人： Intel Corporation

    发明人： Rahul Jain ,  Kyu-Oh Lee ,  Islam A. Salama ,  Amruthavalli P. Alur ,  Wei-Lun K. Jen ,  Yongki Min ,  Sheng C. Li

    IPC分类号： H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L23/538

    摘要： Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.