公开(公告)号：US20140091954A1

公开(公告)日：2014-04-03

申请号：US13629974

申请日：2012-09-28

申请人： Analog Devices, Inc.

发明人： Ning Zhu ,  Hajime Shibata

IPC分类号： H03L7/08 ,  G05F1/10 ,  H03M3/02

CPC分类号： H02M3/06 ,  H03L7/0814 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/0898

摘要： A delay locked loop (DLL) includes a delay line that delays a clock signal to generate a delayed clock signal, a phase frequency detector (PFD) for detecting a phase and/or frequency difference between the clock signal and the delayed clock signal, and a charge pump having an adjustable bias current for converting the phase and/or frequency difference taking into account a bias current adjustment into a control voltage, in which the control voltage controls an amount of delay in the delayed clock signal.

公开(公告)号：US20140085120A1

公开(公告)日：2014-03-27

申请号：US13624802

申请日：2012-09-21

申请人： INVENSENSE, INC.

发明人： Stanley Bo-Ting Wang ,  Derek K. Shaeffer

IPC分类号： H03F1/38 ,  H03M3/02

CPC分类号： H03M3/34

摘要： An embodiment of the invention includes an analog to digital converter including a sigma delta modulator that generates a feedback signal. The sigma delta modulator includes a quantizer responsive to an input signal and the feedback signal and generates a quantizer output. The sigma delta modulator further includes a chopper-stabilized amplifier that provides a reference signal to the sigma delta modulator, and the chopper-stabilized amplifier is stabilized according to a combination of a chopping signal and the quantizer output.

摘要翻译： 本发明的实施例包括一个模数转换器，其包括产生反馈信号的Σ-Δ调制器。 Σ-Δ调制器包括响应于输入信号和反馈信号的量化器，并产生量化器输出。 Σ-Δ调制器还包括一个斩波稳定的放大器，该放大器向Σ-Δ调制器提供参考信号，并且斩波稳定放大器根据斩波信号和量化器输出的组合而被稳定。

公开(公告)号：US20140077978A1

公开(公告)日：2014-03-20

申请号：US13623350

申请日：2012-09-20

申请人： Phuong HUYNH

发明人： Phuong HUYNH

IPC分类号： H03M3/02

CPC分类号： H03M3/02 ,  H03M3/40 ,  H03M3/41

摘要： An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As.

摘要翻译： 提供了改进的正交带通采样Δ-Σ模数转换器，其包括环路滤波器，响应于环路滤波器的A / D和响应于A / D上变频的第一反馈D / A 频率乘第一乘法器和时钟。 第一求和电路响应于第一D / A和RF输入，用于向环路滤波器提供输入。 多个反馈D / AA响应于通过多个乘法器在不同频率中上变频的A / D和用于向环路滤波器提供反馈输入的多个时钟。 环路滤波器包括以级联配置布置的多个谐振器，多个模拟混频器，用于提供通过谐振器传播的误差信号的频移，以及响应于反馈D / A的多个求和电路。

公开(公告)号：US20130293401A1

公开(公告)日：2013-11-07

申请号：US13462345

申请日：2012-05-02

申请人： Paul M. Werking

发明人： Paul M. Werking

IPC分类号： H03M3/02 ,  H03M1/10

CPC分类号： H03M3/388 ,  H03M3/50

摘要： A sigma-delta digital-to-analog converter (SD DAC) exhibits undesirable distortion when implemented in an integrated circuit due to the non-linearity of polysilicon resistors used in the filtering stages of the SD DAC. By using resistors other than polysilicon for the output resistor of an SD DAC, distortion can be reduced or eliminated. Additionally or alternatively, by generating an error correction signal, the distortion can be corrected.

摘要翻译： 由于在SD DAC的滤波级中使用的多晶硅电阻的非线性，因此在集成电路中实现时，Σ-Δ数模转换器（SD DAC）表现出不期望的失真。 通过使用多晶硅之外的电阻作为SD DAC的输出电阻，可以减少或消除失真。 附加地或替代地，通过产生纠错信号，可以校正失真。

公开(公告)号：US20130278454A1

公开(公告)日：2013-10-24

申请号：US13603179

申请日：2012-09-04

申请人： Konstantin Schmid ,  Michael Reinhold ,  Frank Ohnhaeuser

发明人： Konstantin Schmid ,  Michael Reinhold ,  Frank Ohnhaeuser

IPC分类号： H03M3/02

CPC分类号： H03M3/338 ,  H03M3/34 ,  H03M3/43 ,  H03M3/47

摘要： The modulator comprises a first and second integration stages, and a comparator, the first integration stage is fully differential having: an amplifier, sets of input sampling capacitors and feedback capacitors, and the first integration stage is configured to sample the analog input voltage on a set of input capacitors during a first portion of a clock cycle and on a set of input capacitors during a second portion of the clock cycle and to sample the feedback reference voltage on a set of feedback capacitors during the first portion of the clock cycle and on a set of feedback capacitors during the second portion of the clock cycle, and the first set of feedback capacitors and the second set of feedback capacitors are randomly selected out of the plurality of sets of feedback capacitors from cycle to cycle.

摘要翻译： 调制器包括第一和第二积分级和比较器，第一积分级是完全差分的，其具有：放大器，输入采样电容器组和反馈电容器组，并且第一积分级被配置为在模拟输入电压 在时钟周期的第一部分期间的一组输入电容器和在时钟周期的第二部分期间的一组输入电容器，并且在时钟周期的第一部分期间在一组反馈电容器上对反馈参考电压进行采样， 在时钟周期的第二部分期间的一组反馈电容器，以及从周期到周期的多组反馈电容器中随机选择第一组反馈电容器和第二组反馈电容器。

公开(公告)号：US20130194114A1

公开(公告)日：2013-08-01

申请号：US13362565

申请日：2012-01-31

申请人： Rudolf Ritter ,  Markus Schimper ,  Werner Schelmbauer ,  Maurits Ortsmanns

发明人： Rudolf Ritter ,  Markus Schimper ,  Werner Schelmbauer ,  Maurits Ortsmanns

IPC分类号： H03M3/02

CPC分类号： H04B1/123 ,  H03M3/30 ,  H03M3/368 ,  H03M3/424 ,  H03M3/454 ,  H04B1/1036

摘要： An analog-to-digital converter for converting an input signal includes a sigma-delta modulator for receiving an analog modulator input signal and for providing a digital modulator output signal and an interference cancellation loop. The interference cancellation loop includes a digital filter, a digital-to-analog converter, and a signal combiner. The digital filter is configured to amplify the sigma-delta output signal in a frequency band, attenuate the sigma-delta output signal outside the frequency band and a transition band surrounding the frequency band, and provide a filtered digital feedback signal. The digital-to-analog converter is configured to convert the filtered digital signal to a cancellation signal. The signal combiner is configured to combine the input signal with the cancellation signal resulting in the modulator input signal, in order to at least partially cancel interference signal portions within the input signal.

摘要翻译： 用于转换输入信号的模拟 - 数字转换器包括用于接收模拟调制器输入信号并用于提供数字调制器输出信号和干扰消除环路的Σ-Δ调制器。 干扰消除环路包括数字滤波器，数模转换器和信号组合器。 数字滤波器被配置为放大频带中的Σ-Δ输出信号，衰减频带外的Σ-Δ输出信号和围绕频带的过渡带，并提供经滤波的数字反馈信号。 数模转换器被配置为将滤波后的数字信号转换成消除信号。 信号组合器被配置为将输入信号与消除信号组合，导致调制器输入信号，以便至少部分地消除输入信号内的干扰信号部分。

公开(公告)号：US20130106633A1

公开(公告)日：2013-05-02

申请号：US13329983

申请日：2011-12-19

申请人： Dong-Woo Jee ,  Jae-Yoon Sim

发明人： Dong-Woo Jee ,  Jae-Yoon Sim

IPC分类号： H03M3/02

CPC分类号： G04F10/005

摘要： The present invention relates to a time digital converter, and more particularly, to a noise-shaping time to digital converter (TDC) that has a 1-bit output and uses a delta-sigma modulation method. The noise-shaping time to digital converter (TDC) that has the 1-bit output and uses the delta-sigma modulation method in accordance with the present invention eliminates the need for a large number of D flip-flops or counters and a plurality of delay units connected in series to one another because the time to digital converter is fabricated such that a delay element has a resolution of the effective delay time in a semiconductor process, unlike the conventional time to digital converter. Therefore, the time to digital converter of the present invention has an advantage in that an extremely high resolution and high linearity can be achieved with an efficient circuit configuration and low power consumption.

摘要翻译： 时间数字转换器技术领域本发明涉及时间数字转换器，更具体地说，涉及具有1位输出并使用Δ-Σ调制方法的数字转换器（TDC）的噪声整形时间。 具有1位输出并使用根据本发明的Δ-Σ调制方法的数字转换器（TDC）的噪声整形时间消除了对大量D触发器或计数器以及多个 延迟单元彼此串联连接，因为数字转换器的时间被制造成使得延迟元件在半导体处理中具有有效延迟时间的分辨率，这与传统的数字转换器不同。 因此，本发明的数字时钟转换器的优点在于，可以以高效的电路结构和低功耗实现极高的分辨率和高线性度。

公开(公告)号：US20130099949A1

公开(公告)日：2013-04-25

申请号：US13277688

申请日：2011-10-20

申请人： Horst Wagner ,  Udo Karthaus

发明人： Horst Wagner ,  Udo Karthaus

IPC分类号： H03M3/02 ,  H05K13/00

CPC分类号： H03M3/368 ,  H03M3/454 ,  Y10T29/49002

摘要： A delta-sigma modulator (1) for converting a delta-sigma modulator input signal into a sequence of delta-sigma modulator output values comprising an actual delta-sigma modulator output value and at least one preceding delta-sigma modulator output value preceding the actual delta-sigma modulator output value is presented. At least one feedback signal modifier for modifying a at least one first feedback signal in dependence of the actual delta-sigma modulator output value and the at least one preceding delta-sigma modulator output value is provided. By means of the at least one first feedback signal modifier the signal quality of a subsequent final stage (7) can be improved.

摘要翻译： 一种Δ-Σ调制器（1），用于将Δ-Σ调制器输入信号转换成Δ-Σ调制器输出值的序列，其包括实际的Δ-Σ调制器输出值和至少一个之前的Δ-Σ调制器输出值 提出了Δ-Σ调制器的输出值。 提供至少一个反馈信号修正器，用于根据实际的Δ-Σ调制器输出值和至少一个在前的Δ-Σ调制器输出值来修改至少一个第一反馈信号。 通过所述至少一个第一反馈信号调节器，可以改善随后的最后级（7）的信号质量。

公开(公告)号：US20130082766A1

公开(公告)日：2013-04-04

申请号：US13252981

申请日：2011-10-04

申请人： Yi-Lung CHEN

发明人： Yi-Lung CHEN

IPC分类号： H04B1/10 ,  H03M3/02

CPC分类号： H03M3/396 ,  H04B1/30

摘要： The present invention provides a dual mode sigma delta analog to digital converter (ADC), which only in one hardware implementation, used for low IF and near zero IF receiver. The dual mode sigma delta ADC comprises a first switched-capacitor integrator; a second switched-capacitor integrator; a quantizer; a feedback circuit and a mode device. By switching the mode device on or off, one could easily change the configuration of the disclosed ADC to decide the receiving signal falling in low-IF or near zero IF.

摘要翻译： 本发明提供了一种仅在一个硬件实现中用于低IF和近零IF接收机的双模Σ-Δ模数转换器（ADC）。 双模Σ-ΔADC包括第一开关电容积分器; 第二开关电容器积分器; 量化器 反馈电路和模式设备。 通过打开或关闭模式设备，可以轻松地改变所公开的ADC的配置，以确定接收信号落入低IF或接近零IF。

公开(公告)号：US20130015987A1

公开(公告)日：2013-01-17

申请号：US13183438

申请日：2011-07-15

申请人： Ayman Shabra

发明人： Ayman Shabra

IPC分类号： H03M1/12 ,  H03M1/00 ,  H05K13/00 ,  H03M3/02

CPC分类号： H03M3/326 ,  H03M3/39 ,  H04B7/0413 ,  Y10T29/49002

摘要： A multi-input-multi-output-system (MIMO) is provided that includes a first input signal and a second input signal. A plurality of analog-to-digital converter (ADC) cell structures receive as input a combination of the first input signal and the second input signal as well as a combination of quantization noise signals from the respective other ADC cell structures of the plurality of ADC cell structures. The ADC cell structures generate a plurality of first output signals and the noise quantization signals. A plurality of adder modules receive the first output signals and performing either addition or subtraction on a selected combination of the first output signals, the adder modules generate a plurality of second output signals. A plurality of division modules receive the second output signals and perform a division operation on the second output signals by a predetermined factor. The division modules generate a plurality of final output signals of the MIMO.

摘要翻译： 提供了一种包括第一输入信号和第二输入信号的多输入多输出系统（MIMO）。 多个模数转换器（ADC）单元结构作为输入接收第一输入信号和第二输入信号的组合，以及来自多个ADC的各个其它ADC单元结构的量化噪声信号的组合 细胞结构。 ADC单元结构产生多个第一输出信号和噪声量化信号。 多个加法器模块接收第一输出信号并对所选择的第一输出信号的组合执行加法或减法，加法器模块产生多个第二输出信号。 多个分割模块接收第二输出信号，并以预定的因素对第二输出信号执行除法运算。 分割模块产生MIMO的多个最终输出信号。