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公开(公告)号：US10672578B2
公开(公告)日：2020-06-02
申请号：US15754634
申请日：2016-08-25
IPC分类号： H01H47/18 , H03K17/284 , H03K17/30 , H03K17/785 , G01R31/327
摘要： A programmable solid-state relay includes a base module; a configuration module; a control voltage module having an energy storage device; a controller module having at least two microcontrollers, each having an internal EEPROM memory and at least one digital timer; and at least one switch module including at least one switching circuit having first and second switching contacts. The control voltage module is adapted to receive an applied control voltage and to permit pre-selection of an activation voltage level and a de-activation voltage level.
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公开(公告)号：US20200076292A1
公开(公告)日：2020-03-05
申请号：US16499506
申请日：2018-01-19
发明人： Jun TOMISAWA , Akinori NISHIZAWA
IPC分类号： H02M1/08 , H03K17/16 , H03K17/284 , H03K17/687 , H03K17/042
摘要： A programmable decoder (201) includes a counter (204A) whose count value increases for each clock; an address decoder (205A) for converting the count value into an address; a storage (251A) storing a table defining data according to the address converted from the count value; and a latch unit (207) for latching the data according to the address output from the storage (251A). A variable driver (202) includes a plurality of MOS transistors (208), (209), (210). The latch unit (207A) has outputs connected to control electrodes of a plurality of MOS transistors (208), (209), (210). The table defines a plurality of data items in the table so that the driving force of the variable driver (202) increases with an increase of the count value. A counter (20A) updates the count value while the arm control signal is being activated.
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23.发明授权公开(公告)号：US10483961B2
公开(公告)日：2019-11-19
申请号：US15925396
申请日：2018-03-19
申请人： Intel Corporation
发明人： Suyoung Bang , Minki Cho , Pascal Meinerzhagen , Muhammad Khellah
IPC分类号： H03L5/00 , H03K17/16 , H03K17/284 , H03K17/10
摘要： An apparatus is provided which comprises: a first power supply rail to provide a first power supply voltage; a second power supply rail to provide a second power supply voltage, wherein the first power supply voltage is higher than the second power supply voltage; a first circuitry coupled to the first and second supply rails, wherein the first circuitry is to operate using the first supply voltage, and wherein the first circuitry is to inject charge on to the second power supply rail in response to a droop indication; and a second circuitry to detect voltage droop on the second power supply rail, wherein the second circuitry is to generate the droop indication for the first circuitry.
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公开(公告)号：US10425074B2
公开(公告)日：2019-09-24
申请号：US15496400
申请日：2017-04-25
发明人： Sakae Nakajima
IPC分类号： H03K17/284 , H03K17/082 , H01L27/02 , H01L27/092 , H02H5/04 , H03K17/22 , H02H9/02 , H02H3/08
摘要： There has been a problem in semiconductor apparatuses of related art in which a circuit operation cannot be returned after a reverse current occurred. In one embodiment, a semiconductor apparatus includes a timer block configured to count up a count value to a predetermined value in response to a control signal being enabled, the control signal instructing a power MOS transistor to be turned on, and a protection transistor including a drain connected to a gate of the power MOS transistor, a source and a back gate connected to a source of the power MOS transistor, and an epitaxial layer in which the power MOS transistor is formed, the epitaxial layer being supplied with a power supply voltage. The protection transistor short-circuits the source and gate of the power MOS transistor in response to an output voltage of the power MOS transistor meeting a predetermined condition and the count value reaching the predetermined value. The timer block resets the count value when the output voltage of the power MOS transistor no longer meets the predetermined condition.
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公开(公告)号：US10277026B2
公开(公告)日：2019-04-30
申请号：US15938265
申请日：2018-03-28
摘要： A power converter connected between a direct current power supply and a load, the power converter including a switching unit energizing the load based on inputted control signal, a voltage detector detecting a voltage of the direct current power supply, and a protection operation portion detecting a steep elevation of the voltage and performing protection operation to stop a switching operation by the switching unit, wherein the protection operation portion includes an addition circuit adding a predetermined voltage to the voltage detected by the voltage detector and a delay time generator connected to an output of the addition circuit, and wherein the protection operation is performed when a difference between the voltage detected by the voltage detector and an output voltage of the delay time generator reaches a certain value.
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公开(公告)号：US20180367134A1
公开(公告)日：2018-12-20
申请号：US16061921
申请日：2016-12-02
IPC分类号： H03K17/10 , H02M1/088 , H03K17/284 , H03K17/693
摘要： This application relates to methods and apparatus for voltage balancing of voltage source converters and especially for voltage balancing of clamp capacitors of a director switch of a voltage source converter. Typically a director switch of a voltage source converter includes series connected director switch units, each having a semiconductor switching element. In some voltage source converter designs each director switch unit has an associated clamp capacitor. The method of controls involves switching the semiconductor switching elements of the director switch units to transition the director switch between conducting and non-conducting states where the timing of switching of a semiconductor switching element is based on the voltage level of the associated clamp capacitor and also the degree of any voltage imbalance between the clamp capacitors of the director switch units. A control apparatus may determine suitable switching control signals.
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公开(公告)号：US10141845B2
公开(公告)日：2018-11-27
申请号：US15366264
申请日：2016-12-01
摘要： Disclosed examples provide DC-DC converters and control circuits to provide high and low-side driver signals and to selectively adjust a delay time between a low-side switching device turning off and a high-side switching device turning on according to a comparator signal, including a clocked comparator circuit referenced to a switching node to sample the voltage across the high-side switching device in response to a first edge of the high-side driver signal, and to generate the comparator signal indicating a polarity of the sampled high-side switch voltage to facilitate zero voltage switching of the high-side switching device.
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公开(公告)号：US20180331657A1
公开(公告)日：2018-11-15
申请号：US15948889
申请日：2018-04-09
IPC分类号： H03F1/02 , H03K17/16 , H03F1/22 , H03F3/193 , H03F3/217 , H03F3/24 , G10H1/057 , H03K17/693 , H03K17/10 , H03K17/0812 , H04B1/04 , H03K17/284 , H02M1/00
CPC分类号： H03F1/0222 , G10H1/057 , H02M2001/0045 , H03F1/22 , H03F3/193 , H03F3/2171 , H03F3/245 , H03F2200/102 , H03F2200/336 , H03F2203/7236 , H03F2203/7239 , H03K17/08122 , H03K17/102 , H03K17/162 , H03K17/284 , H03K17/693 , H03K2217/0054 , H04B1/04 , H04B2001/0408 , H04B2001/045
摘要： Aspects of this disclosure relate to a radio frequency system that includes an envelope generator configured to generate an envelope signal corresponding to an envelope of a radio frequency signal and at least two radio frequency components coupled to the envelope generator. One of the radio frequency components is a radio frequency switch configured to pass the radio frequency signal. The radio frequency switch is configured to receive the envelope signal to cause intermodulation distortion associated with the radio frequency switch to be reduced.
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公开(公告)号：US20180293952A1
公开(公告)日：2018-10-11
申请号：US15573948
申请日：2017-05-15
发明人： Min He , Haixia Xu , Dongxu Han , Meng Li
IPC分类号： G09G3/36 , H03K17/284
CPC分类号： G09G3/3677 , G09G2230/00 , G09G2300/0408 , G09G2310/08 , G11C19/28 , H03K17/284
摘要： A gate integrated driving circuit for a display panel. The gate integrated driving circuit may comprise N reset circuits. For each of the N reset circuits, a first terminal thereof may be coupled to a reference signal terminal a second terminal thereof may be coupled to signal output terminals of a set of input and output circuits respectively, a third terminal thereof may be coupled to control terminals of driving circuits of the set of input and output circuits respectively, and a fourth terminal thereof may be coupled to a clock signal terminal coupled to input terminals of the driving circuits of the set of input and output circuits respectively. N may be an integer of at least 3. The set of input and output circuits may contain two or more input and output circuits.
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公开(公告)号：US20180254160A1
公开(公告)日：2018-09-06
申请号：US15754634
申请日：2016-08-25
IPC分类号： H01H47/18 , G01R31/327 , H03K17/284 , H03K17/30 , H03K17/785
CPC分类号： H01H47/18 , G01R31/3278 , H03K17/284 , H03K17/302 , H03K17/785
摘要： A programmable solid-state relay includes a base module; a configuration module; a control voltage module having an energy storage device; a controller module having at least two microcontrollers, each having an internal EEPROM memory and at least one digital timer; and at least one switch module including at least one switching circuit having first and second switching contacts. The control voltage module is adapted to receive an applied control voltage and to permit pre-selection of an activation voltage level and a de-activation voltage level.
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