公开(公告)号：US20050135138A1

公开(公告)日：2005-06-23

申请号：US10989096

申请日：2004-11-12

Applicant: David Turgis

Inventor： David Turgis

IPC: G11C17/10 ,  G11C17/14 ,  G11C17/00

CPC classification number: G11C17/14 ,  G11C17/10

Abstract: A ROM-type memory is provided that includes a matrix of memory cells made up of rows and columns, with each row allowing storage of a page of MUX words of N bits. An address decoder decodes addresses in order to extract the page to be read. At the output of the matrix, N multiplexers are each coupled to the columns that correspond to one of the bits of the output stage. An N-bit output stage includes at least one inverter, with each of the inverters being connected to the output of one of the multiplexers so as to restore inverted values of information to be stored to correct values. The inverted values are stored in all of the memory cells of all of the columns coupled to the one multiplexer. Storing the inverted values makes it possible to store less “0” values within the matrix and further makes LVS testing of the ROM memory considerably easier. Also provided is a method for sequentially checking groups of memory cells.

Abstract translation: 提供了一种ROM型存储器，其包括由行和列组成的存储器单元的矩阵，每行允许存储N位的MUX字的页面。 地址解码器解码地址以便提取要读取的页面。 在矩阵的输出端，N个多路复用器分别耦合到对应于输出级的一个位的列。 N位输出级包括至少一个反相器，其中每个反相器连接到多路复用器中的一个的输出，以便恢复待存储的信息的反相值以校正值。 反相值存储在耦合到一个多路复用器的所有列的所有存储单元中。 存储反向值可以在矩阵内存储较少的“0”值，并进一步使ROM存储器的LVS测试更容易。 还提供了用于顺序检查存储器单元组的方法。

公开(公告)号：US06898538B2

公开(公告)日：2005-05-24

申请号：US10025372

申请日：2001-12-19

Applicant: François Tailliet

Inventor： François Tailliet

IPC: G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/32 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50

CPC classification number: G11C29/028 ,  G11C7/1045 ,  G11C7/20 ,  G11C7/22 ,  G11C16/04 ,  G11C16/32 ,  G11C29/02 ,  G11C29/14 ,  G11C29/50 ,  G11C29/50012

Abstract: A method for adjusting a duration of an internal timing signal in an integrated circuit with a value close to a typical value of the duration may include activating the internal timing signal in the integrated circuit and sequentially sending calibration values to an input of the integrated circuit. The expiration of the internal timing signal may determine the last calibration value received or being received, and the calibration data may be applied to a device for adjusting the duration of the internal timing signal.

Abstract translation: 用于以接近于持续时间的典型值的值调整集成电路中的内部定时信号的持续时间的方法可以包括激活集成电路中的内部定时信号并且顺序地将校准值发送到集成电路的输入。 内部定时信号的到期可以确定接收或正在接收的最后一个校准值，并且校准数据可以应用于用于调整内部定时信号的持续时间的设备。

公开(公告)号：US20050104660A1

公开(公告)日：2005-05-19

申请号：US10944679

申请日：2004-09-17

Applicant: Philippe Sirito-Olivier

Inventor： Philippe Sirito-Olivier

IPC: H03F3/45

CPC classification number: H03F3/45085 ,  H03F2203/45636

Abstract: A differential amplifier includes a pair of first and second transistors connected together. The first transistor includes a first conduction terminal, and a second conduction terminal forming a first output node of the amplifier. The second transistor includes a first conduction terminal connected to the first conduction terminal of the first transistor, and a second conduction terminal forming a second output node of the amplifier. A first inductive load is connected between the first output node and a supply reference, and a second inductive load is connected between the second output node and the supply reference. A limiting network limits output voltages on the first and second output nodes, and includes a first resistor connected to the first output node, and a second resistor connected to the second output node. The first and second resistors also connected together in series at a common intermediate node. A first analog switch is connected to the first resistor and to the supply reference, and a second analog switch connected to the second resistor and the supply reference via the first analog switch. The first and second analog switches are turned on when a voltage on the common intermediate node exceeds a threshold.

Abstract translation: 差分放大器包括连接在一起的一对第一和第二晶体管。 第一晶体管包括第一导电端子和形成放大器的第一输出节点的第二导电端子。 第二晶体管包括连接到第一晶体管的第一导通端子的第一导电端子和形成放大器的第二输出节点的第二导电端子。 第一感性负载连接在第一输出节点和供电基准之间，第二电感负载连接在第二输出节点和供电基准之间。 限制网络限制第一和第二输出节点上的输出电压，并且包括连接到第一输出节点的第一电阻器和连接到第二输出节点的第二电阻器。 第一和第二电阻器也在公共中间节点串联连接在一起。 第一模拟开关连接到第一电阻器和电源基准，以及通过第一模拟开关连接到第二电阻器和电源基准的第二模拟开关。 当公共中间节点上的电压超过阈值时，第一和第二模拟开关导通。

公开(公告)号：US20050094424A1

公开(公告)日：2005-05-05

申请号：US10978316

申请日：2004-10-29

Applicant: Bertrand Rivet

Inventor： Bertrand Rivet

IPC: H02M7/21 ,  H02M1/08 ,  H02M3/28 ,  H02M3/335 ,  H02M7/217

CPC classification number: H02M7/217 ,  H02M1/083

Abstract: A circuit for controlling a switch to be controlled in unidirectional fashion while the voltage present there across is an A.C. voltage, including circuitry for delaying the switch turning-on with respect to a zero crossing of the voltage there across, and circuitry for triggering the switch turning-off after its turning on, at the end of a predetermined time interval plus or minus an error time controlled by the duty cycle of the A.C. voltage across the switch, in one or several previous periods. The control circuit applies to the forming of a rectifying circuit by the switch.

Abstract translation: 一种用于控制开关被控制的电路，同时存在于其上的电压是AC电压，包括用于相对于其跨越的电压过零点延迟开关导通的电路，以及用于触发开关的电路 在预定的时间间隔结束时，在一个或多个先前的周期中，通过开关上的交流电压的占空比控制的误差时间结束，关闭。 控制电路适用于通过开关形成整流电路。

公开(公告)号：US20050080967A1

公开(公告)日：2005-04-14

申请号：US10966623

申请日：2004-10-14

Applicant: Gilles Ries ,  Jean-Francois Agaesse

Inventor： Gilles Ries ,  Jean-Francois Agaesse

IPC: G06F13/364 ,  G06F13/14

CPC classification number: G06F13/364

Abstract: A method for arbitrating access to a resource shared by several electronic elements. Each element is allocated a first counting value and a first penalty, the first counting value is decremented in synchronization with a clock signal, and is incremented by a value equal to the first penalty every time the element is selected for an access cycle. When several elements are simultaneously waiting to access the shared resource, an element is selected to access the resource if its first counting value is lower than or equal to a determined threshold, and is lower than the first counting values of the other elements having sent an access request.

Abstract translation: 一种用于仲裁访问由几个电子元件共享的资源的方法。 每个元件被分配第一计数值和第一罚分，第一计数值与时钟信号同步地递减，并且在每次为访问周期选择元件时，增加等于第一惩罚的值。 当多个元素同时等待访问共享资源时，如果元素的第一计数值低于或等于确定的阈值，则选择元素来访问资源，并且低于已发送的其他元素的第一计数值 访问请求。

公开(公告)号：US20050078503A1

公开(公告)日：2005-04-14

申请号：US10921365

申请日：2004-08-18

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C8/20 ,  G11C11/22 ,  G11C16/22

CPC classification number: G11C16/22

Abstract: A memory circuit comprising a memory area for storing data, a non-volatile memory area for storing at least one identification code, and a pin for storing the identification code in the non-volatile memory area. The memory circuit further comprising a programmable register in which a programmable state is fixed, wherein the programmable state indicates if the identification code has been stored in the non-volatile memory area, and a logic module which blocks any subsequent changes to the identification code fixed in the non-volatile memory area in response to the programmable state in the programmable register indicating that the identification code has been stored in the non-volatile area. The invention also relates to an associated method. The invention is useful particularly to avoid fraudulent reprogramming of the area containing the identification code. The invention also relates to an associated method.

Abstract translation: 一种存储电路，包括用于存储数据的存储区域，用于存储至少一个识别码的非易失性存储区域和用于将所述识别码存储在所述非易失性存储区域中的引脚。 存储器电路还包括其中可编程状态是固定的可编程寄存器，其中可编程状态指示识别码是否已被存储在非易失性存储器区域中，以及逻辑模块，其阻止对固定的识别码的任何后续改变 响应于所述可编程寄存器中的所述可编程状态指示所述识别码已被存储在所述非易失性区域中，在所述非易失性存储器区域中。 本发明还涉及一种相关联的方法。 本发明特别适用于避免包含识别码的区域的欺骗性重新编程。 本发明还涉及一种相关联的方法。

公开(公告)号：US06870238B2

公开(公告)日：2005-03-22

申请号：US10478177

申请日：2002-05-17

Applicant: Juan Exposito ,  Remi Brechignac ,  Julien Vittu

Inventor： Juan Exposito ,  Remi Brechignac ,  Julien Vittu

IPC: G02B6/42 ,  H01L31/0203 ,  H01L31/0232 ,  H01L27/14

CPC classification number: H01L27/14618 ,  G02B6/4277 ,  H01L31/0203 ,  H01L31/02325 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2924/16195 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An optical semiconductor package includes an optical semiconductor component (8), a front face of which has an optical sensor (10), and encapsulation defining a cavity in which the optical component is placed and having external electrical connection (11) of this optical semiconductor component (8). The encapsulation (2, 5) includes a glass pane letting light through to the optical sensor. The encapsulation (2, 5) includes electromagnetic screening (23, 24, 28) made of an electrically conductive material, that is externally connectable, this screening being electrically isolated in the optical semiconductor package from the electrical connection of the optical semiconductor component (8).

Abstract translation: 光学半导体封装包括光学半导体部件（8），其前表面具有光学传感器（10），并且封装限定了光学部件放置在其中并具有该光学半导体的外部电连接（11）的空腔 组件（8）。 封装（2,5）包括一个使光通过光学传感器的玻璃板。 封装（2,5）包括由外部可连接的导电材料制成的电磁屏蔽（23,24,28），该屏蔽在光学半导体封装中与光学半导体部件（8）的电连接电隔离 ）。

公开(公告)号：US20050029661A1

公开(公告)日：2005-02-10

申请号：US10839761

申请日：2004-05-05

Applicant: Michel Vallet ,  Sylvain Kritter

Inventor： Michel Vallet ,  Sylvain Kritter

IPC: G01R31/307 ,  H01L23/58 ,  H01L29/40 ,  G01R31/26

CPC classification number: G01R31/307 ,  H01L22/32

Abstract: An integrated circuit is provided that includes an active region and at least one interconnect part. The interconnect part is located above the active region, and includes a plurality of metallization levels and at least one test pad. The test pad is located in one of the metallization levels that is beneath a top one of the metallization levels. In a preferred embodiment, the test pad is located beneath supply lines. Also provided is a method for testing such an integrated circuit.

Abstract translation: 提供了一种集成电路，其包括有源区和至少一个互连部。 互连部分位于有源区上方，并且包括多个金属化层和至少一个测试焊盘。 测试垫位于金属化水平的顶部之下的金属化水平之一。 在优选实施例中，测试垫位于供应线下方。 还提供了一种用于测试这种集成电路的方法。

公开(公告)号：US20050026417A1

公开(公告)日：2005-02-03

申请号：US10867382

申请日：2004-06-14

Applicant: Jerome Teysseyre

Inventor： Jerome Teysseyre

IPC: H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/3114 ,  H01L21/563 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/19041 ,  H01L2224/83 ,  H01L2224/81 ,  H01L2924/00

Abstract: Process for fabricating semiconductor components, and semiconductor component, in which a support plate comprises, at various locations, portions provided with respective electrical connection means having electrical connection regions on a front face and having through-holes located in proximity or adjacently to the portions. An integrated-circuit chip is fastened to the front face of each portion of the support plate by means of electrical connection balls. On one side, the electrical connection balls are connected to electrical connection regions of the front face of this plate and, on the other side, to electrical connection pads on the rear face of this integrated-circuit chip, in positions such that one edge of the rear face of each integrated-circuit chip faces at least one through-hole. A curable liquid fill material is delivered in the through-holes so as to at least partly fills a space defined between this support plate and each integrated-circuit chip, respectively.

Abstract translation: 用于制造半导体部件的工艺和半导体部件，其中支撑板在各个位置处包括设置有在前表面上具有电连接区域并且具有位于所述部分附近或相邻的通孔的各个电连接装置的部分。 集成电路芯片通过电连接球紧固到支撑板的每个部分的前表面。 在一侧，电连接球连接到该板的正面的电连接区域，另一侧连接到该集成电路芯片的背面上的电连接焊盘， 每个集成电路芯片的后表面面向至少一个通孔。 可固化液体填充材料在通孔中被输送，以分别至少部分地填充在该支撑板和每个集成电路芯片之间限定的空间。

公开(公告)号：US20050010851A1

公开(公告)日：2005-01-13

申请号：US10858866

申请日：2004-06-02

Applicant: Hubert Degoirat ,  Loic Parlier

Inventor： Hubert Degoirat ,  Loic Parlier

IPC: G06F11/10 ,  H03M13/37 ,  H03M13/00

CPC classification number: H03M13/37

Abstract: A decoding and error correcting method is applicable to a secured code word that may have an error relative to an initial secured code word. The method includes an error correcting step, and a decoding step using a decoding function. The decoding step may be carried out before the error correcting step, and includes applying the decoding function to the secured code word to obtain a secured decoded word containing a coded error. The method reduces the decoding and error correcting time of the secured code word.

Abstract translation: 解码和纠错方法适用于可能具有相对于初始安全码字的错误的安全码字。 该方法包括纠错步骤和使用解码功能的解码步骤。 解码步骤可以在错误校正步骤之前执行，并且包括将解码功能应用于安全码字以获得包含编码错误的安全解码字。 该方法减少了安全码字的解码和纠错时间。