公开(公告)号：US20240030115A1

公开(公告)日：2024-01-25

申请号：US18352962

申请日：2023-07-14

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Loic Pierre Louis RENARD

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/42

CPC classification number: H01L23/49811 ,  H01L24/32 ,  H01L24/48 ,  H01L23/3107 ,  H01L23/42 ,  H01L2224/48091 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/1306 ,  H01L2924/01029 ,  H01L2924/182

Abstract: The present disclosure is directed to a power package with copper plating terminals. The power package includes at least two terminals coupled to a semiconductor die. An area of a first terminal is greater than an area of a second terminal. The first and second terminals extend to a first and second conductive layers in a backside of the package. A third conductive layer is coupled to a backside surface of the die that is coplanar with the first and second conductive layers. The terminals and conductive layers are copper plating. A first molding compound covers the die and terminals, while a second molding compound fills distances between the die and the extensions of the terminals. The copper plating and the molding compounds enhance the performance of the packaged device in a high-power circuit. In addition, robustness of the package is enhanced compared with conventional packages including wire bonding.

公开(公告)号：US11828877B2

公开(公告)日：2023-11-28

申请号：US17015521

申请日：2020-09-09

Applicant: STMicroelectronics PTE LTD

Inventor： Jing-En Luan

IPC: G01S7/481

CPC classification number: G01S7/4813

Abstract: The present disclosure is directed to an optical sensor package with a first assembly and a second assembly with an encapsulant extending between and coupling the first assembly and the second assembly. The first assembly includes a first substrate, a first die on the first substrate, a transparent material on the first die, and an infrared filter on the transparent material. The second assembly includes a second substrate, a second die on the second substrate, a transparent material on the second die, and an infrared filter on the transparent material. Apertures are formed through the encapsulant aligned with the first die and the second die. The first die is configured to transmit light through one aperture, wherein the light reflects off an object to be detected and is received at the second die through another one of the apertures.

公开(公告)号：US11828875B2

公开(公告)日：2023-11-28

申请号：US17551001

申请日：2021-12-14

Applicant: STMICROELECTRONICS PTE LTD

Inventor： David Gani

IPC: G01S7/18 ,  G01J1/42 ,  G01S7/481 ,  G01S17/08 ,  G01S7/493 ,  G01S7/497 ,  G01S7/487 ,  G01S17/04 ,  G01S7/48

CPC classification number: G01S7/4808 ,  G01J1/4204 ,  G01S7/4813 ,  G01S7/4814 ,  G01S7/4816 ,  G01S7/4876 ,  G01S7/493 ,  G01S7/497 ,  G01S17/04 ,  G01S17/08

Abstract: A semiconductor package that is a proximity sensor includes a light transmitting die, a light receiving die, an ambient light sensor, a cap, and a substrate. The light receiving die and the light transmitting die are coupled to the substrate. The cap is coupled to the substrate forming a first chamber around the light transmitting die and a second chamber around the light receiving die. The cap further includes a recess with contact pads. The ambient light sensor is mounted within the recess of the cap and coupled to the contact pads. The cap includes electrical traces that are coupled to the contact pads within the recess coupling the ambient light sensor to the substrate. By utilizing a cap with a recess containing contact pads, a proximity sensor can be formed in a single semiconductor package all while maintaining a compact size and reducing the manufacturing costs of proximity sensors.

公开(公告)号：US20230307302A1

公开(公告)日：2023-09-28

申请号：US18184436

申请日：2023-03-15

Applicant: STMICROELECTRONICS LTD ,  STMICROELECTRONICS PTE LTD

Inventor： David GANI ,  Hui-Tzu Wang

IPC: H01L23/04 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/04 ,  H01L25/0655 ,  H01L24/32 ,  H01L2924/16151 ,  H01L2924/16788 ,  H01L2224/32225

Abstract: A semiconductor package includes a silicon substrate with an active surface and an inactive surface. A semiconductor device, such as an image, light, or optical sensor, is formed in the active surface and disposed on the substrate. A glass plate is coupled to the substrate with adhesive. The glass plate includes a sensor area that corresponds to the area of the semiconductor device and holes through the glass plate that are generally positioned around the sensor area of the glass plate. During formation of the package, the holes through the glass plate allow gas released by the adhesive to escape the package and prevent formation of a gas bubble.

公开(公告)号：US20230245992A1

公开(公告)日：2023-08-03

申请号：US18081248

申请日：2022-12-14

Applicant: STMicroelectronics PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/822 ,  H01L21/56

CPC classification number: H01L24/24 ,  H01L23/49805 ,  H01L21/822 ,  H01L21/565 ,  H01L21/561 ,  H01L21/568 ,  H01L24/19 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/19 ,  H01L2224/24226 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/73209 ,  H01L2224/16227 ,  H01L2924/182

Abstract: An integrated circuit die includes a semiconductor substrate, an interconnect layer including bonding pads, and a passivation layer covering the interconnect layer and including openings at the bonding pads. A conductive redistribution layer including conductive lines and conductive vias is supported by the passivation layer. An insulating layer covers the conductive redistribution layer and the passivation layer. Channels formed in an upper surface of the insulating layer delimit pedestal regions in the insulating layer. A through via extends from an upper surface of each pedestal region through the pedestal region and the insulating layer to reach and make contact with a portion of the conductive redistribution layer. A metal pad is formed at the upper surface of each pedestal region in contact with its associated through via. The metal pads for leads of a quad-flat no-lead (QFN) type package.

公开(公告)号：US20230238341A1

公开(公告)日：2023-07-27

申请号：US18079610

申请日：2022-12-12

Applicant: STMicroelectronics Pte Ltd

Inventor： Churn Weng YIM ,  Maurizio Gabriele CASTORINA ,  Voon Cheng NGWAN ,  Yean Ching YONG ,  Ditto ADNAN ,  Fadhillawati TAHIR

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L2224/05073 ,  H01L2224/05573 ,  H01L2224/022 ,  H01L2224/0219 ,  H01L2224/03019 ,  H01L2224/03466 ,  H01L2224/03614 ,  H01L2224/03622 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05647

Abstract: A bonding pad for an integrated circuit is formed by a stack of bonding pad layers. A lower bonding pad layer is supported by a bonding pad support layer. A passivation layer extends over the lower bonding pad layer and includes a passivation opening at a portion of an upper surface of the lower bonding pad layer. An upper bonding pad layer rests on said passivation layer and in the passivation opening in contact with the lower bonding pad layer.

公开(公告)号：US20230029799A1

公开(公告)日：2023-02-02

申请号：US17874052

申请日：2022-07-26

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L23/31 ,  H01L27/146

Abstract: The present disclosure is directed to embodiments of sensor package including a doped resin on respective surfaces and sidewalls of a transparent portion, a sensor die, and a support structure extending from the transparent portion to the sensor die. The support structure suspends the transparent portion over a sensor of the sensor die. The doped resin is doped with an additive material, and the additive material is activated by exposing the doped resin to a laser. The doped resin is exposed to the laser forming conductive layers extending along the doped resin for providing electrical connections within the sensor package and to electronic components external to the embodiments of the sensor die packages. The conductive layers are at least partially covered by a non-conductive layer.

公开(公告)号：US20220393022A1

公开(公告)日：2022-12-08

申请号：US17730895

申请日：2022-04-27

Applicant: STMicroelectronics PTE LTD ,  STMicroelectronics (Tours) SAS

Inventor： Shin Phay LEE ,  Voon Cheng NGWAN ,  Frederic LANOIS ,  Fadhillawati TAHIR ,  Ditto ADNAN

IPC: H01L29/739 ,  H01L29/40 ,  H01L29/66

Abstract: A trench in a semiconductor substrate is lined with a first insulation layer. A hard mask layer deposited on the first insulation layer is used to control performance of an etch that selectively removes a first portion of the first insulating layer from an upper trench portion while leaving a second portion of first insulating layer in a lower trench portion. After removing the hard mask layer, an upper portion of the trench is lined with a second insulation layer. An opening in the trench that includes a lower open portion delimited by the second portion of first insulating layer in the lower trench portion and an upper open portion delimited by the second insulation layer at the upper trench portion, is then filled by a single deposition of polysilicon material forming a unitary gate/field plate conductor of a field effect rectifier diode.

公开(公告)号：US20220352133A1

公开(公告)日：2022-11-03

申请号：US17714822

申请日：2022-04-06

Applicant: STMICROELECTRONICS PTE LTD

Inventor： Jing-En LUAN

IPC: H01L25/16 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

Abstract: The present disclosure is directed to embodiments of optical sensor packages. For example, at least one embodiment of an optical sensor package includes a light-emitting die, a light-receiving die, and an interconnect substrate within a first resin. A first transparent portion is positioned on the light-emitting die and the interconnect substrate, and a second transparent portion is positioned on the light-receiving die and the interconnect substrate. A second resin is on the first resin, the interconnect substrate, and the first and second transparent portions, respectively. The second resin partially covers respective surfaces of the first and second transparent portions, respectively, such that the respective surfaces are exposed from the second resin.

公开(公告)号：US20220352057A1

公开(公告)日：2022-11-03

申请号：US17729452

申请日：2022-04-26

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Pte Ltd

Inventor： Roberto TIZIANI ,  Laurent HERARD

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/13

Abstract: A substrate includes electrically-conductive tracks. A semiconductor chip is arranged on the substrate and electrically coupled to selected ones of the electrically-conductive tracks. Containment structures are provided at selected locations on the electrically-conductive tracks, where the containment structures have respective perimeter walls defining respective cavities. Each cavity is configured to accommodate a base portion of a pin holder. These pin holders are soldered to the electrically-conductive tracks within the cavities defined by the containment structures. Each containment structure may be formed by a ring of resist material configured to receive solder and maintain the pin holders in a desired alignment position.