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    Transistor Gate Profile Optimization
    291.
    发明申请
    Transistor Gate Profile Optimization 有权

    公开(公告)号：US20240379672A1

    公开(公告)日：2024-11-14

    申请号：US18780798

    申请日：2024-07-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Sheng Lai ,  Wei-Chung Sun ,  Li-Ting Chen ,  Kuei-Yu Kao ,  Chih-Han Lin

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

    Abstract: A device includes a plurality of fin structures that each protrude vertically upwards out of a substrate and each extend in a first direction in a top view. A gate structure is disposed over the fin structures. The gate structure extends in a second direction in the top view. The second direction is different from the first direction. The fin structures have a fin pitch equal to a sum of: a dimension of one of the fin structures in the second direction and a distance between an adjacent pair of the fin structures in the second direction. An end segment of the gate structure extends beyond an edge of a closest one of the fin structures in the second direction. The end segment has a tapered profile in the top view or is at least 4 times as long as the fin pitch in the second direction.

    Semiconductor Device Package and Methods of Manufacture
    292.
    发明申请
    Semiconductor Device Package and Methods of Manufacture 有权

    公开(公告)号：US20240379645A1

    公开(公告)日：2024-11-14

    申请号：US18779561

    申请日：2024-07-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Jiun Yi Wu ,  Chen-Hua Yu

    IPC: H01L25/18 ,  H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00

    Abstract: A method includes forming a redistribution structure on a carrier substrate, coupling a first side of a first interconnect structure to a first side of the redistribution structure using first conductive connectors, where the first interconnect structure includes a core substrate, where the first interconnect structure includes second conductive connectors on a second side of the first interconnect structure opposite the first side of the first interconnect structure, coupling a first semiconductor device to the second side of the first interconnect structure using the second conductive connectors, removing the carrier substrate, and coupling a second semiconductor device to a second side of the redistribution structure using third conductive connectors, where the second side of the redistribution structure is opposite the first side of the redistribution structure.

    MULTI-LEVEL STACKING OF WAFERS AND CHIPS
    294.
    发明申请
    MULTI-LEVEL STACKING OF WAFERS AND CHIPS 有权

    公开(公告)号：US20240379614A1

    公开(公告)日：2024-11-14

    申请号：US18782253

    申请日：2024-07-24

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Ming-Fa Chen ,  Cheng-Feng Chen ,  Sung-Feng Yeh ,  Chuan-An Cheng

    IPC: H01L23/00 ,  H01L21/78 ,  H01L25/00 ,  H01L25/065

    Abstract: In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.

    REDUCTION OF CRACKS IN PASSIVATION LAYER
    295.
    发明申请
    REDUCTION OF CRACKS IN PASSIVATION LAYER 有权

    公开(公告)号：US20240379593A1

    公开(公告)日：2024-11-14

    申请号：US18771809

    申请日：2024-07-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-An Liu ,  Wen-Chiung Tu ,  Yuan-Yang Hsiao ,  Kai Tak Lam ,  Chen-Chiu Huang ,  Zhiqiang Wu ,  Dian-Hau Chen

    IPC: H01L23/00

    Abstract: Methods and semiconductor structures are provided. A semiconductor structure according to the present disclosure includes a plurality of transistors, an interconnect structure electrically coupled to the plurality of transistors, a metal feature disposed over the interconnect structure and electrically isolated from the plurality of transistors, an insulation layer disposed over the metal feature, and a first redistribution feature and a second redistribution feature disposed over the insulation layer. A space between the first redistribution feature and the second redistribution feature is disposed directly over at least a portion of the metal feature.

    NOVEL MIM STRUCTURE
    296.
    发明申请
    NOVEL MIM STRUCTURE 有权

    公开(公告)号：US20240379532A1

    公开(公告)日：2024-11-14

    申请号：US18784638

    申请日：2024-07-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chun-huan WEI ,  Pin Yu HSU ,  Szu-Yuan CHEN ,  Po-June CHEN ,  Kuan-Yu CHEN

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

    Abstract: Disclosed is a method of manufacturing a three dimensional (3D) metal-insulator-metal (MIM) capacitor in the back end of line, which can provide large and tunable capacitance values and meanwhile, does not interfere with the existing BEOL fabrication process. In one embodiment, a method for fabricating a semiconductor device includes: forming a first conductive feature on a semiconductor substrate; forming a second conductive feature on the semiconductor substrate; forming a first via structure over the first conductive feature; forming a first metallization structure over the first via structure, wherein the first metallization structure is conductively coupled to the first conductive feature through the first via structure; forming a conductive etch stop structure on the first metallization structure; forming a first via hole above the conductive etch stop structure and a second via hole above the second conductive feature, wherein the first via hole exposes the conductive etch stop structure and the second via hole is deeper than the first via hole; and forming a capacitor in the second via hole.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    298.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20240379458A1

    公开(公告)日：2024-11-14

    申请号：US18784863

    申请日：2024-07-25

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Jhon-Jhy LIAW

    IPC: H01L21/8238 ,  H01L21/311 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

    Abstract: A method for manufacturing a semiconductor device includes forming first and second semiconductor fins extending upwardly from a substrate; forming a dielectric fin between the first and second semiconductor fins; forming a shallow trench isolation (STI) structure laterally surrounding lower portions of the first and second semiconductor fins and the dielectric fin; forming a gate strip extending across upper portions of the first semiconductor fin, the dielectric fin, and the second semiconductor fin; patterning the gate strip to form a first gate structure extending across the first semiconductor fin and a second gate structure extending across the second semiconductor fin while leaving the dielectric fin uncovered; and after patterning the gate strip, depositing a high-k dielectric material over the dielectric fin and in contact with a longitudinal end of the first gate structure and a longitudinal end of the second gate structure.

    Methods For Forming Source/Drain Features
    299.
    发明申请
    Methods For Forming Source/Drain Features 有权

    公开(公告)号：US20240379455A1

    公开(公告)日：2024-11-14

    申请号：US18779731

    申请日：2024-07-22

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： I-Hsieh Wong ,  Wei-Yang Lee ,  Chia-Pin Lin ,  Yuan-Ching Peng

    IPC: H01L21/8238 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: A semiconductor structure and a method of forming the same are provided. In an embodiment, a method includes receiving a workpiece comprising a substrate, an active region protruding from the substrate, and a dummy gate structure disposed over a channel region of the active region. The method also includes forming a trench in a source/drain region of the active region, forming a sacrificial structure in the trench, conformally depositing a dielectric film over the workpiece, performing a first etching process to etch back the dielectric film to form fin sidewall (FSW) spacers extending along sidewalls of the sacrificial structure, performing a second etching process to remove the sacrificial structure to expose the trench, forming an epitaxial source/drain feature in the trench such that a portion of the epitaxial source/drain feature being sandwiched by the FSW spacers, and replacing the dummy gate structure with a gate stack.

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