公开(公告)号：US11651479B2

公开(公告)日：2023-05-16

申请号：US17131570

申请日：2020-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Chang-Che Tsai ,  Tsung-Han Chiang

IPC: G06T3/40 ,  G06T5/00 ,  G06T5/50

CPC classification number: G06T5/009 ,  G06T3/4007 ,  G06T3/4015 ,  G06T5/50 ,  G06T2207/20221

Abstract: An image processing method and an image processing device is provided. The processing device comprises memory and a processor configured to receive a frame of color filtered image data comprising pixels which are spatially multiplexed according to a plurality of different light exposures, resample the color values as different frames of pixels for the plurality of different light exposures, fuse the resampled frames of pixels for the plurality of different light exposures into a frame of pixels according to a HDR format and color interpolate the fused frame of pixels. The processor is configured to interpolate, for each resampled frame, missing pixel color values based on the color values of adjacent resampled pixels in a same resampled frame. The color interpolated fused frame of pixels is processed in an image processing pipeline and converted to a YUV color space.

公开(公告)号：US20230145626A1

公开(公告)日：2023-05-11

申请号：US17521601

申请日：2021-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Miguel Rodriguez ,  Stephen Victor Kosonocky ,  Kaushik Mazumdar

IPC: G01R31/40 ,  H03M3/00 ,  H03K5/24 ,  H03K19/0175

CPC classification number: G01R31/40 ,  H03M3/30 ,  H03K5/24 ,  H03K19/017509

Abstract: A power supply monitor includes a delta-sigma modulator including an input receiving a binary number and an output providing a pulse-density modulated signal, the delta-sigma modulator operable to scale the pulse-density modulated signal based on the binary number. A fast droop detector circuit includes a level shifter providing the modulated signal referenced to a clean supply voltage. A lowpass filter is coupled between the level shifter and a comparator. The comparator produces a droop detection signal at said output responsive to a monitored supply voltage dropping below a predetermined level relative to the filtered signal.

公开(公告)号：US20230143760A1

公开(公告)日：2023-05-11

申请号：US17521483

申请日：2021-11-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kelley ,  Paul Moyer

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/0868

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/0868

Abstract: Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between threads. By comparing either the cache line sharing parameters or the counter to corresponding thresholds, a policy is set which defines whether copies of shared cache lines at such indices are to be retained in the L3 cache.

公开(公告)号：US20230143622A1

公开(公告)日：2023-05-11

申请号：US18152022

申请日：2023-01-09

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： DAVID A. ROBERTS ,  GREG SADOWSKI ,  STEVEN RAASCH

IPC: H01L23/34 ,  G05B15/02 ,  H01L25/065 ,  G06F1/20

CPC classification number: H01L23/34 ,  G05B15/02 ,  H01L25/0657 ,  G06F1/20 ,  H01L2225/06589

Abstract: Exemplary embodiments provide thermal wear spreading among a plurality of thermal die regions in an integrated circuit or among dies by using die region wear-out data that represents a cumulative amount of time each of a number of thermal die regions in one or more dies has spent at a particular temperature level. In one example, die region wear-out data is stored in persistent memory and is accrued over a life of each respective thermal region so that a long term monitoring of temperature levels in the various die regions is used to spread thermal wear among the thermal die regions. In one example, spreading thermal wear is done by controlling task execution such as thread execution among one or more processing cores, dies and/or data access operations for a memory.

公开(公告)号：US20230140100A1

公开(公告)日：2023-05-04

申请号：US18089209

申请日：2022-12-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander M. Potapov ,  Skyler Jonathon Saleh ,  Swapnil P. Sakharshete ,  Vineet Goel

IPC: G06T3/40

Abstract: A processing device is provided which includes memory and a processor. The processor is configured to receive an input image having a first resolution, generate at least one linear down-sampled version of the input image via a linear upscaling network, generate at least one non-linear down-sampled version of the input image via a non-linear upscaling network, extract a first feature map from the at least one linear down-sampled version of the input image, and extract a second feature map from the at least one non-linear down-sampled version of the input image. The processor is also configured to convert the at least one linear down-sampled version of the input image and the at least one non-linear down-sampled version of the input image into pixels of an output image having a second resolution higher than the first resolution using the first feature map and the second feature map.

公开(公告)号：US20230138518A1

公开(公告)日：2023-05-04

申请号：US17514776

申请日：2021-10-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul J. Moyer

IPC: G06F12/0891 ,  G06F12/084 ,  G06F13/16 ,  G06F9/30

Abstract: Techniques for performing cache operations are provided. The techniques include for a memory access class, detecting a threshold number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state; in response to the detecting, treating first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state; detecting a reset event for the memory access class; and in response to detecting the reset event, treating second coherence state agnostic requests for cache lines for the memory class as coherence state agnostic requests.

公开(公告)号：US20230136815A1

公开(公告)日：2023-05-04

申请号：US17514723

申请日：2021-10-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Luke Jereme Whitaker ,  Edoardo Prete

IPC: G06F1/08 ,  H03K23/00 ,  H03K17/693

Abstract: A system and method for efficiently generating clock signals are described. In various implementations, an integrated circuit includes multiple clock frequency dividers both at its I/O boundaries and across its die. A clock frequency divider utilizes a first clock divider and a second clock divider that receive input clock signals with an initial phase difference between them. The first clock divider and the second clock divider generate output clock signals that have frequencies that are a fraction of the frequencies of the received input clock signals. The second clock divider uses a combined multiplexer and flip-flop (combined mux-flop) circuit. The combined mux-flop circuit receives a reset signal that is asserted asynchronously with respect to an input clock signal received by the second clock divider. The second clock divider generates an output clock signal that has the initial phase difference with an output clock signal of the first clock divider.

公开(公告)号：US11640840B2

公开(公告)日：2023-05-02

申请号：US17360958

申请日：2021-06-28

Applicant: Advanced Micro Devices, Inc.

Inventor： SeyedMohammad SeyedzadehDelcheh ,  Gabriel H. Loh

IPC: G11C11/40 ,  G11C11/06 ,  G11C11/4078 ,  G11C11/408 ,  G06F12/1018 ,  G06F3/06 ,  G11C11/406 ,  G11C11/4076

Abstract: An electronic device includes a memory having a plurality of memory rows and a memory refresh functional block that performs a victim row refresh operation. For the victim row refresh operation, the memory refresh functional block selects one or more victim memory rows that may be victims of data corruption caused by repeated memory accesses in a specified group of memory rows near each of the one or more victim memory rows. The memory refresh functional block then individually refreshes each of the one or more victim memory rows.

公开(公告)号：US20230129642A1

公开(公告)日：2023-04-27

申请号：US17507597

申请日：2021-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Ankit Kamleshbhai Zalawadiya ,  Krishnan-Talkad Sukumar ,  Ravinder Reddy Rachala

IPC: G01R31/40 ,  H03K3/03 ,  H03K3/037 ,  G01R19/00 ,  G06F1/28 ,  G06F1/04

Abstract: A system and method for efficiently measuring on-die power supply voltage are described. In various implementations, an integrated circuit includes power supply monitors across a die of the integrated circuit. A power supply monitor receives a power supply voltage and generates a code indicating a value of the power supply voltage. A first ring oscillator receives the power supply voltage and a pulse used as an enable signal. A pulse generator of the power supply monitor takes into account the process, voltage and temperature (PVT) characteristics of the integrated circuit by including at least a second ring oscillator and a modulus counter that receives an output of the second ring oscillator. Therefore, the pulse generated by the pulse generator is PVT dependent and increases gain of the power supply monitor.

公开(公告)号：US11635967B2

公开(公告)日：2023-04-25

申请号：US17032307

申请日：2020-09-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sateesh Lagudu ,  Allen H. Rush ,  Michael Mantor ,  Arun Vaidyanathan Ananthanarayan ,  Prasad Nagabhushanamgari ,  Maxim V. Kazakov

IPC: G06F15/80 ,  G06F9/38 ,  G06F13/28 ,  G06F13/40

Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that broadcast sets of the parameter values to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor includes single-instruction-multiple-data (SIMD) units including subsets of the processor element arrays in corresponding rows, workgroup processors (WGPs) including subsets of the SIMD units, and a memory fabric configured to interconnect with an external memory that stores the parameter values. The memory interfaces broadcast the parameter values to the SIMD units that include the processor element arrays in rows associated with the memory interfaces and columns of processor element arrays that are implemented across the SIMD units in the WGPs. The memory interfaces access the parameter values from the external memory via the memory fabric.