公开(公告)号：US20070025644A1

公开(公告)日：2007-02-01

申请号：US11191762

申请日：2005-07-28

Applicant: Ghy-Bin Wang ,  Ming-Sung Huang ,  Inn Liu

Inventor： Ghy-Bin Wang ,  Ming-Sung Huang ,  Inn Liu

IPC: G06K9/32

CPC classification number: G06T3/4007

Abstract: A graphics display adapter has a row interpolator circuit connected to receive the source pixel data synchronized at a first clock rate and to interpolate groups of pixels of row at a second clock rate. A row interpolated storage device receives and retains interpolated source pixel data of each row at the second clock rate. A column interpolator circuit extracts the interpolated source pixel data at a third clock rate. The column interpolator circuit then interpolates groupings of the interpolated source pixel data at the third clock rate and transmits the destination graphic pixel data for display. The second clock rate maybe equal to the first clock rate or the faster of the first and third clock rates.

Abstract translation: 图形显示适配器具有连接用于接收以第一时钟速率同步的源像素数据并以第二时钟速率内插行的像素组的行内插器电路。 行内插存储装置以第二时钟速率接收并保持每行的内插源像素数据。 列插值器电路以第三时钟速率提取内插源像素数据。 然后，列插值器电路以第三时钟速率内插内插源像素数据的分组，并发送用于显示的目的地图形像素数据。 第二个时钟速率可能等于第一个时钟速率或第一个和第三个时钟速率的速度。

公开(公告)号：US20060228223A1

公开(公告)日：2006-10-12

申请号：US11094280

申请日：2005-03-31

Applicant: Lien-Hsun Chen ,  Ming-Chen Wu ,  Tsung-Bin Wang

Inventor： Lien-Hsun Chen ,  Ming-Chen Wu ,  Tsung-Bin Wang

IPC: F04B49/06

CPC classification number: F04D29/582 ,  F04D27/004

Abstract: A system and a method for control of fan rotational speed are applied in an electronic device with a fan for temperature adjustment. The electronic device at least records a first fan rotational speed of the fan when a temperature of the fan is higher than a predetermined temperature interval and a second fan rotational speed of the fan when the temperature of the fan is lower than the temperature interval. A fan rotational speed during operation of the fan is recorded. The electronic device detects a temperature of an exothermic object being adjusted by the fan, and outputs a temperature parameter. The electronic device determines whether the temperature parameter belongs to the temperature interval and accordingly adjusts the fan rotational speed of the fan. The system and method make change of the fan rotational speed less sensitive to oscillations in system temperature and prolong the lifetime of the fan.

Abstract translation: 在具有用于温度调节的风扇的电子设备中应用用于控制风扇转速的系统和方法。 当风扇的温度比风扇的温度低于温度间隔时，当风扇的温度高于预定温度区间和风扇的第二风扇转速时，电子设备至少记录风扇的第一风扇转速。 记录风扇运转时的风扇转速。 电子设备检测由风扇调节的放热物体的温度，并输出温度参数。 电子设备确定温度参数是否属于温度间隔，从而调节风扇的风扇转速。 该系统和方法使风扇转速的变化对系统温度的振荡较不敏感，延长了风扇的使用寿命。

公开(公告)号：US20060226489A1

公开(公告)日：2006-10-12

申请号：US11095938

申请日：2005-03-30

Applicant: Bin Wang ,  Todd Humes

Inventor： Bin Wang ,  Todd Humes

IPC: H01L29/76

CPC classification number: H01L27/115 ,  G11C16/0441 ,  G11C16/045 ,  H01L27/11521 ,  H01L27/11558

Abstract: Retention-enhanced, programmable, shared floating gate logic circuits are employed as NVM cells. In one embodiment, the NVM cell is formed by a dual transistor logic gate circuit with a shared floating gate. The logic circuit is an inverter. The shared floating gate is doped partially or completely with p-type impurities to enhance retention. A charge adjustment circuit is arranged to inject and remove electrons to and from the shared floating gate determining the output of the logic gate circuit when supply voltage is applied to the logic gate circuit. In another embodiment, four transistors are employed to form another logic circuit such as a NOR gate or a NAND gate.

Abstract translation: 采用保持增强型可编程共享浮栅逻辑电路作为NVM单元。 在一个实施例中，NVM单元由具有共享浮动栅极的双晶体管逻辑门电路形成。 逻辑电路是一个逆变器。 共享浮栅部分或完全掺杂有p型杂质以增强保留性。 电荷调整电路被布置成当向逻辑门电路施加电源电压时，向共享浮置栅极注入和去除电子，以确定逻辑门电路的输出。 在另一个实施例中，采用四个晶体管来形成诸如或非门或与非门的另一个逻辑电路。

公开(公告)号：US20060222629A1

公开(公告)日：2006-10-05

申请号：US11317548

申请日：2005-12-23

Applicant: David Weiner ,  William Williams ,  Bin Wang

Inventor： David Weiner ,  William Williams ,  Bin Wang

IPC: A61K48/00 ,  A61K39/12 ,  A61K31/44 ,  A61K31/40 ,  A61K31/138 ,  A61K31/137

CPC classification number: A61K38/193 ,  A61K39/00 ,  A61K39/0011 ,  A61K39/0225 ,  A61K39/12 ,  A61K39/205 ,  A61K39/21 ,  A61K39/29 ,  A61K39/292 ,  A61K48/0008 ,  A61K2039/53 ,  A61K2039/545 ,  A61K2039/55511 ,  A61K2039/55566 ,  C07K14/005 ,  C12N15/87 ,  C12N2730/10122 ,  C12N2730/10134 ,  C12N2740/13022 ,  C12N2740/16122 ,  C12N2740/16134 ,  C12N2740/16222 ,  C12N2740/16234 ,  C12N2740/16322 ,  C12N2740/16334 ,  C12N2760/20122 ,  C12N2760/20134 ,  C12N2770/24222 ,  C12N2770/24234 ,  Y02A50/464 ,  Y02A90/26

Abstract: Methods of introducing genetic material into cells of an individual and compositions and kits for practicing the same are disclosed. The methods comprise the steps of contacting cells of an individual with a polynucleotide function enhancer and administering to the cells, a nucleic acid molecule that is free of retroviral particles. The nucleic acid molecule comprises a nucleotide sequence that encodes a protein that comprises at least one epitope that is identical or substantially similar to an epitope of a pathogen antigen or an antigen associated with a hyperproliferative or autoimmune disease, a protein otherwise missing from the individual due to a missing, non-functional or partially functioning gene, or a protein that produces a therapeutic effect on an individual. Methods of prophylactically and therapeutically immunizing an individual against HIV am disclosed. Pharmaceutical compositions and kits for practicing methods of the present invention are disclosed.

Abstract translation: 公开了将遗传物质引入个体细胞的方法和用于实施其的组合物和试剂盒。 所述方法包括使个体的细胞与多核苷酸功能增强子接触并向细胞施用不含逆转录病毒颗粒的核酸分子的步骤。 核酸分子包含编码蛋白质的核苷酸序列，该蛋白质包含与病原体抗原或与过度增殖或自身免疫疾病相关的抗原的表位相同或基本相似的至少一个表位， 涉及缺失的，非功能的或部分功能的基因或对个体产生治疗作用的蛋白质。 公开了预防和治疗个体免受HIV的方法。 公开了用于本发明的实践方法的药物组合物和试剂盒。

公开(公告)号：US20060209598A1

公开(公告)日：2006-09-21

申请号：US11084214

申请日：2005-03-17

Applicant: Bin Wang ,  Chih-Hsin Wang ,  William Colleran

Inventor： Bin Wang ,  Chih-Hsin Wang ,  William Colleran

IPC: G11C16/04

CPC classification number: G11C16/10

Abstract: NVM arrays include rows and columns of NVM cells comprising a floating gate, dual transistor, inverter storage element. Supply voltage for selected storage elements is turned off during a programming and an erase mode. Isolation transistors for each NVM cell or for each row of NVM cells may be used to control the supply voltage.

Abstract translation: NVM阵列包括包括浮动栅极，双晶体管，逆变器存储元件的NVM单元的行和列。 在编程和擦除模式期间，所选存储元件的电源电压关闭。 可以使用每个NVM单元或每行NVM单元的隔离晶体管来控制电源电压。

公开(公告)号：US06229726B1

公开(公告)日：2001-05-08

申请号：US09498742

申请日：2000-02-07

Applicant: Gyh-Bin Wang ,  Chih-Tung Wang ,  Tah-Kang Joseph Ting

Inventor： Gyh-Bin Wang ,  Chih-Tung Wang ,  Tah-Kang Joseph Ting

IPC: G11C502

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C5/04 ,  G11C7/1048 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit formed on a semiconductor substrate having multiple input/output signal paths such that the semiconductor substrate can be mounted to more than one package type. The integrated circuit formed on the semiconductor substrate has at least three pluralities of input output connector pads. The first plurality of input/output connector pads is placed on the semiconductor substrate and is attached to a first functional circuit of the integrated circuit. The second and third pluralities of input/output connector pads are placed on the semiconductor substrate and are attached to a second functional circuit of the integrated circuit. The third plurality of input/output connector pads is placed in an area separated from the first and second pluralities of input/output connector pads. Each input/output connector pads of the third plurality of input/output connector pads is connected to a corresponding input/output connector pad of the second plurality of input/output connector pads and thus to the second functional circuit. If the semiconductor substrate is mounted in a first package type, the second plurality of input/output connector pads is bonded to pins of the first package type to connect the second functional circuit to the external circuit, and the third plurality of input/output connector pads remain unbonded. If the semiconductor substrate is mounted in a second package type, the third plurality of input/output connector pads is bonded to pins of the second package type to connect the second functional circuit to the external circuit and the second plurality of input/output connector pads remain unbonded.

Abstract translation: 一种形成在具有多个输入/输出信号路径的半导体衬底上的集成电路，使得半导体衬底可以安装到多于一种封装形式。 形成在半导体衬底上的集成电路具有至少三个输入输出连接器焊盘。 第一组多个输入/输出连接器焊盘被放置在半导体衬底上并且被附接到集成电路的第一功能电路。 第二和第三多个输入/输出连接器焊盘放置在半导体衬底上，并附接到集成电路的第二功能电路。 第三多个输入/输出连接器焊盘放置在与第一和第二多个输入/输出连接器焊盘分离的区域中。 第三多个输入/输出连接器焊盘的每个输入/输出连接器焊盘连接到第二多个输入/输出连接器焊盘的相应输入/输出连接器焊盘，并且因此连接到第二功能电路。 如果半导体衬底被安装在第一封装类型中，则第二多个输入/输出连接器焊盘接合到第一封装类型的引脚，以将第二功能电路连接到外部电路，并且第三多个输入/输出连接器 垫片保持未粘合。 如果半导体衬底被安装在第二封装类型中，则第三个多个输入/输出连接器焊盘接合到第二封装类型的引脚，以将第二功能电路连接到外部电路，而第二个多个输入/输出连接器焊盘 保持未粘合

公开(公告)号：US06197755B1

公开(公告)日：2001-03-06

申请号：US09321461

申请日：1999-05-27

Applicant: Richard A. Carrano ,  Bin Wang ,  David B. Weiner

Inventor： Richard A. Carrano ,  Bin Wang ,  David B. Weiner

IPC: A61K317088

CPC classification number: C07K14/005 ,  A61K38/193 ,  A61K39/0011 ,  A61K39/0225 ,  A61K39/12 ,  A61K39/21 ,  A61K39/29 ,  A61K39/292 ,  A61K48/00 ,  A61K2039/53 ,  A61K2039/55511 ,  A61K2039/55522 ,  C12N15/85 ,  C12N15/87 ,  C12N2730/10134 ,  C12N2740/14022 ,  C12N2740/14034 ,  C12N2740/15034 ,  C12N2740/16134 ,  C12N2740/16222 ,  C12N2740/16234 ,  C12N2770/24034 ,  C12N2770/24222 ,  C12N2770/24234 ,  C12N2800/108 ,  Y02A50/464

Abstract: Methods of introducing genetic material into cells of an individual and compositions and kits for practicing the same are disclosed. The methods comprise the steps of contacting cells of an individual with a genetic vaccine facilitator and administering to the cells, a nucleic acid molecule that is free of retroviral particles. The nucleic acid molecule comprises a nucleotide sequence that encodes a protein that comprises at least one epitope that is identical or substantially similar to an epitope of a pathogen antigen or an antigen associated with a hyperproliferative or autoimmune disease, a protein otherwise missing from the individual due to a missing, non-functional or partially functioning gene, or a protein that produce a therapeutic effect on an individual. Methods of prophylactically and therapeutically immunizing an individual against HIV are disclosed. Pharmaceutical compositions and kits for practicing methods of the present invention are disclosed.

Abstract translation: 公开了将遗传物质引入个体细胞的方法和用于实施其的组合物和试剂盒。 所述方法包括使个体的细胞与基因疫苗促进剂接触并向细胞施用不含逆转录病毒颗粒的核酸分子的步骤。 核酸分子包含编码蛋白质的核苷酸序列，该蛋白质包含与病原体抗原或与过度增殖或自身免疫疾病相关的抗原的表位相同或基本相似的至少一个表位， 涉及缺失的，非功能的或部分功能的基因或对个体产生治疗作用的蛋白质。 公开了预防和治疗个体免受HIV感染的方法。 公开了用于本发明的实践方法的药物组合物和试剂盒。

公开(公告)号：US6130853A

公开(公告)日：2000-10-10

申请号：US50216

申请日：1998-03-30

Applicant: Ming-Hung Wang ,  Gyh-Bin Wang ,  Chun Shiah

Inventor： Ming-Hung Wang ,  Gyh-Bin Wang ,  Chun Shiah

IPC: G11C7/10 ,  G11C8/10 ,  G11C8/00

CPC classification number: G11C7/1015 ,  G11C7/1018 ,  G11C7/1042 ,  G11C7/1072 ,  G11C8/10

Abstract: Circuits and a method are disclosed for a semiconductor memory which decode from a system supplied input address two outputs which are either adjacent or boundary adjacent to each other. The two decoded outputs derived from the input address select then, in one cycle, two locations in a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM). The circuits producing the two decoded outputs allow for sequential and interleaved mode, for data bursts of various lengths, and for addressing of redundant columns.

Abstract translation: 公开了一种半导体存储器的电路和方法，该半导体存储器从系统提供的输入地址中解码两个相邻或相邻边界的输出。 从输入地址导出的两个解码输出在一个周期中选择双倍数据速率同步动态随机存取存储器（DDR SDRAM）中的两个位置。 产生两个解码输出的电路允许顺序和交错模式，用于各种长度的数据突发以及冗余列的寻址。

公开(公告)号：US6064613A

公开(公告)日：2000-05-16

申请号：US221964

申请日：1998-12-28

Applicant: Gyh-Bin Wang

Inventor： Gyh-Bin Wang

IPC: G11C7/06 ,  G11C7/02

CPC classification number: G11C7/062 ,  G11C2207/063

Abstract: A fast CMOS sense amplifier for semiconductor memories is disclosed. The memory sense amplifier configuration is comprised of differential pre-sense amplifier stage and a sense amplifier second stage. The pre-sense amplifier stage is composed of two sections with feedback between the sections which reduces the output swing by means of a clamping action, therefore improving output switching recovery time in response to differential input. The feedback between the sections is provided by cross connecting the sub outputs of each section to the gate of a clamping transistor at each section. The reduced recovery time produces reduced delay at the output which speeds up the operation of the sense amplifier. Additionally, the clamping devices have the effect of reducing the average DC current in the pre-sense amplifier.

Abstract translation: 公开了一种用于半导体存储器的快速CMOS读出放大器。 存储器读出放大器配置包括差分预读放大器级和读出放大器第二级。 预读放大器级由两部分组成，其中部分之间具有反馈，借助于钳位动作来减小输出摆幅，从而根据差分输入改善输出开关恢复时间。 各部分之间的反馈通过将每个部分的子输出交叉连接到每个部分的钳位晶体管的栅极来提供。 缩短的恢复时间在输出端产生减小的延迟，从而加速读出放大器的工作。 此外，钳位装置具有减小预读放大器中的平均直流电流的效果。

公开(公告)号：US6022595A

公开(公告)日：2000-02-08

申请号：US792044

申请日：1997-01-31

Applicant: John F. McDonald ,  Toh-Ming Lu ,  Bin Wang ,  Guang Rong Yang

Inventor： John F. McDonald ,  Toh-Ming Lu ,  Bin Wang ,  Guang Rong Yang

IPC: B05D1/00 ,  B05D7/24 ,  C23C16/44 ,  C08J7/06

CPC classification number: B05D1/60 ,  C23C16/44 ,  B05D1/007

Abstract: A method of depositing a polymer film onto a semiconductor wafer is provided which includes the steps of connecting the wafer to one terminal of a voltage source, connecting an electrode to an other pole of the voltage source and placing the electrode and substrate in superposed orientation to form a parallel plate capacitor, wherein an electric field is produced between the electrode and substrate. The parallel plate capacitor is placed in a chamber where pressure andc temperature are maintained at predetermined levels and gaseous monomers of the desired film to be polymerized are introduced into the chamber. The gaseous monomers are then permitted to flow between the electrode and wafer while the voltage of the electric field is maintained at a level sufficient to polarize the monomers without breaking their chemical bonds wherein the polarized monomers react to form a polymer film on the wafer at an enhanced rate.

Abstract translation: 提供了一种在半导体晶片上沉积聚合物膜的方法，其包括以下步骤：将晶片连接到电压源的一个端子，将电极连接到电压源的另一个极，并将电极和衬底放置成叠置的方向 形成平行板电容器，其中在电极和基板之间产生电场。 将平行板电容器放置在压力和温度保持在预定水平的室中，并将待聚合的所需膜的气态单体引入室中。 然后允许气态单体在电极和晶片之间流动，同时电场的电压保持在足以使单体极化的水平，而不破坏其化学键，其中极化单体在晶片上反应形成聚合物膜， 增加率。