公开(公告)号：US20010012191A1

公开(公告)日：2001-08-09

申请号：US09751300

申请日：2000-12-28

Applicant: STMicroelectronics S.A.

Inventor： Francois Tailliet

IPC: H02H009/00

CPC classification number: H01L27/0266

Abstract: The protection device for an interconnection line of an integrated circuit includes a charge flow-off device connected between the interconnection line to be protected and the substrate of the integrated circuit. The protection device also includes a dummy interconnection line ANT to activate the flow-off device. The protection device is active throughout the manufacture of the integrated circuit.

Abstract translation: 用于集成电路的互连线路的保护装置包括连接在待保护的互连线与集成电路的基板之间的充电流失装置。 保护装置还包括虚拟互连线ANT以激活流失装置。 保护装置在整个集成电路的制造过程中是有效的。

公开(公告)号：US20010011914A1

公开(公告)日：2001-08-09

申请号：US09765501

申请日：2001-01-18

Applicant: STMicroelectronics S.A.

Inventor： Alain Pomet

IPC: H03K005/01

CPC classification number: G06F13/426

Abstract: A device for the regeneration of a clock signal uses a reference clock signal given by an internal oscillator to measure the number of reference clock pulses between the first two synchronization pulses sent by an external serial bus or USB at the beginning of each transaction. Thus a rough measurement N is obtained of the USB clock signal to be regenerated. The delay of each of these two synchronization pulses with respect to the previous pulse of the reference clock signal is measured. This delay is computed with respect to an internally defined time unit. On the basis of the measurement of these two delays, and the measurement of the number of reference clock periods, and knowing the measurement n of the period of the reference clock signal in the time unit, the period of the USB clock signal to be regenerated is computed with precision.

Abstract translation: 用于再生时钟信号的装置使用由内部振荡器给出的参考时钟信号来测量在每个事务开始时由外部串行总线或USB发送的前两个同步脉冲之间的参考时钟脉冲的数量。 因此，获得要再生的USB时钟信号的粗略测量N. 测量这两个同步脉冲中相对于参考时钟信号的先前脉冲的延迟。 相对于内部定义的时间单位计算该延迟。 基于这两个延迟的测量和参考时钟周期的数量的测量，并且知道时间单位中的参考时钟信号的周期的测量n，将要再生的USB时钟信号的周期 是精确计算的。

公开(公告)号：US11086000B2

公开(公告)日：2021-08-10

申请号：US16000512

申请日：2018-06-05

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Research & Development) Limited

Inventor： Victor Macela ,  Ed Hawkins ,  Olivier Pothier ,  Manu Alibay

IPC: G01S7/48 ,  G01S7/4865 ,  G01S17/66 ,  G06F3/01 ,  G01S17/88 ,  G01S17/58 ,  G01S17/04 ,  G01S17/894

Abstract: A method for acquiring tracking points belonging to a trajectory of a target object in motion, includes: emitting a radiation towards the target object; receiving a reflection of the radiation from the target object in respective fields of view of each detection zone of a network of detection zones; processing the reflection by determining distances separating the target object from an origin point by measuring a time of flight of the radiation in each detection zone; determining a degree of coverage of each detection zone; and estimating, based on the distances and on the degree of coverage of each detection zone, a position of a tracking point corresponding to a position of an extremity of the target object inside a respective detection zone chosen in a direction of motion of the target object.

公开(公告)号：US10727799B2

公开(公告)日：2020-07-28

申请号：US16428413

申请日：2019-05-31

Applicant: STMicroelectronics S.A.

Inventor： Renald Boulestin

IPC: H03G3/30 ,  H03F3/19 ,  H03K5/24 ,  H04B1/06

Abstract: A variable gain amplifier includes a pair of amplification and recentering branches. Each branch includes: a resistive element of variable resistance configured to be driven by a variable gain controller; a digitally-driven variable current source configured to be driven by a compensation current driver unit; a first transistor comprising a gate terminal coupled to an input terminal of the variable gain amplifier, and a source terminal coupled to a first terminal of the resistive element; and a second transistor comprising a gate terminal coupled to a drain terminal of the first transistor, and a source terminal coupled to an output terminal of the variable gain amplifier.

公开(公告)号：US10447230B2

公开(公告)日：2019-10-15

申请号：US15653014

申请日：2017-07-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.A.

Inventor： Frédéric Gianesello ,  Romain Pilard ,  Cédric Durand

IPC: H01F27/28 ,  H03H7/42 ,  H01F27/38 ,  H01L23/522 ,  H01F27/29 ,  H01F27/40 ,  H04W88/02

Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.

公开(公告)号：US20170221948A1

公开(公告)日：2017-08-03

申请号：US15489265

申请日：2017-04-17

Applicant: STMicroelectronics S.A. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Axel Crocherie ,  Michel Marty ,  Jean-Luc Huguenin ,  Sébastien Jouan

IPC: H01L27/146 ,  H01L29/66

CPC classification number: H01L29/66977 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14629 ,  H01L27/14645 ,  H01L27/14685 ,  H01L2027/11892 ,  H04N2209/045

Abstract: An integrated image sensor may include adjacent pixels, with each pixel including an active semiconductor region including a photodiode, an antireflection layer disposed above the photodiode, a dielectric region disposed above the antireflection layer, an optical filter disposed above the dielectric region, and a diffraction grating disposed in the antireflection layer. The diffraction grating includes an array of pads.

公开(公告)号：US09385424B2

公开(公告)日：2016-07-05

申请号：US13920237

申请日：2013-06-18

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Pierre Bar ,  Laurent Dussopt ,  Jean-François Carpentier

IPC: H01Q1/50 ,  H01L23/66 ,  H01Q1/24 ,  H01Q9/04 ,  H01Q23/00 ,  H01L23/552 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/552 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05166 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/15788 ,  H01Q1/243 ,  H01Q1/50 ,  H01Q9/0457 ,  H01Q13/106 ,  H01Q19/10 ,  H01Q23/00 ,  H04B1/3833 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941

Abstract: The three-dimensional integrated structure including a support element, an interface device connected to the support element by first electrically conductive connection, an integrated circuit arranged between the support element and the interface device and connected to the interface device by second electrically conductive connection, a filler region between the second electrically conductive connection and between the interface device and the integrated circuit, and an antenna, having a radiating element in electromagnetic coupling with an excitation element through the interconnection of a slot, the antenna being distributed over the interface device and the integrated circuit.

Abstract translation: 三维一体化结构包括支撑元件，通过第一导电连接连接到支撑元件的接口装置，布置在支撑元件和接口装置之间并通过第二导电连接连接到接口装置的集成电路， 所述第二导电连接之间和所述接口装置与所述集成电路之间的填充区域，以及天线，所述天线具有通过所述插槽的互连与激励元件电磁耦合的辐射元件，所述天线分布在所述接口装置上， 集成电路。

公开(公告)号：US09323716B2

公开(公告)日：2016-04-26

申请号：US14329226

申请日：2014-07-11

Applicant: STMicroelectronics S.A.

Inventor： Joël Cambonie

IPC: G06F15/78 ,  G06F13/36 ,  G06F15/173 ,  G06F15/80 ,  G06F9/38 ,  G06F13/368

CPC classification number: G06F15/7867 ,  G06F9/3885 ,  G06F13/368 ,  G06F15/173 ,  G06F15/17381 ,  G06F15/803

Abstract: A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.

Abstract translation: 一种具有N个级别的可重构分层计算机架构，其中N是大于1的整数值，其中所述N个级别包括第一级，包括第一计算块，所述第一级包括第一数据输入，第一数据输出和多个计算节点， 第一连接机构，每个计算节点包括输入端口，功能单元和输出端口，所述第一连接机构能够将每个输出端口连接到彼此的计算节点的输入端口; 以及第二级，包括第二计算块，包括第二数据输入，第二数据输出和通过第二连接装置互连的多个第一计算块，用于选择性地连接每个第一计算块和第二计算块的第一数据输出 数据输入到每个第一数据输入端，并且用于选择性地将每个第一数据输出连接到第二数据输出。

公开(公告)号：US20160026811A1

公开(公告)日：2016-01-28

申请号：US14871873

申请日：2015-09-30

Applicant: STMICROELECTRONICS S.A.

Inventor： Albert Martinez ,  William Orlando

IPC: G06F21/62 ,  G06F21/60 ,  G06F21/79 ,  G06F12/14 ,  G06F21/52

CPC classification number: G06F21/62 ,  G06F12/1408 ,  G06F12/1483 ,  G06F21/52 ,  G06F21/602 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/033 ,  G06F2221/2105

Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.

公开(公告)号：US20150214210A1

公开(公告)日：2015-07-30

申请号：US14599167

申请日：2015-01-16

Applicant: STMICROELECTRONICS S.A.

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat

IPC: H01L27/02 ,  H01L27/06 ,  H01L27/12

CPC classification number: H01L27/0248 ,  H01L27/0262 ,  H01L27/0623 ,  H01L27/1203 ,  H01L29/7436 ,  H01L29/747

Abstract: An electronic device includes a first device terminal and a second device terminal. A first and a second thyristor are reverse-connected between the two device terminals. A first and a second MOS transistor are respectively coupled between the conduction electrodes (emitters and collectors) of the two NPN transistors of the two thyristors. A third MOS transistor is coupled between the emitters of the two NPN bipolar transistors of the two thyristors and a fourth MOS transistor is coupled between the bases of the two PNP bipolar transistors of the two thyristors. A gate region is common to all the MOS transistors and a semiconductor substrate region includes the substrates of all the MOS transistors

Abstract translation: 电子设备包括第一设备终端和第二设备终端。 第一和第二晶闸管反向连接在两个器件端子之间。 第一和第二MOS晶体管分别耦合在两个晶闸管的两个NPN晶体管的导通电极（发射极和集电极）之间。 第三MOS晶体管耦合在两个晶闸管的两个NPN双极晶体管的发射极之间，第四个MOS晶体管耦合在两个晶闸管的两个PNP双极晶体管的基极之间。 栅极区域对于所有MOS晶体管是公共的，并且半导体衬底区域包括所有MOS晶体管的衬底