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    Implementing robust readback capture in a programmable integrated circuit
    301.
    发明授权
    Implementing robust readback capture in a programmable integrated circuit 有权

    公开(公告)号：US10169264B1

    公开(公告)日：2019-01-01

    申请号：US15639752

    申请日：2017-06-30

    Applicant: Xilinx, Inc.

    Inventor： Michelle E. Zeng ,  Subodh Kumar ,  Uma Durairajan ,  Weiguang Lu ,  Karthy Rajasekharan ,  Kumar Rahul

    IPC: G06F13/16 ,  H03K19/177 ,  G06F3/06 ,  G06F13/40 ,  G11C7/10 ,  G01R31/3185

    Abstract: In an example, a memory circuit in a programmable integrated circuit (IC) includes: a control port and a clock port; a configurable random access memory (RAM) having a control input and a clock input; input multiplexer logic coupled to the control input and the clock input; and a state machine coupled to the input multiplexer logic and configuration logic of the programmable IC, the state machine configured to: in response to being enabled by the configuration logic, control the input multiplexer logic to switch a connection of the control input from the control port to the state machine and, subsequently, switch a connection of the clock input from the clock port to a configuration clock source; and in response to being disabled by the configuration logic, control the input multiplexer logic to switch the connection of the clock input from the configuration clock source to the clock port and, subsequently, switch the connection of the control input from the state machine to the control port.

    DYNAMIC ELEMENT MATCHING IN AN INTEGRATED CIRCUIT
    303.
    发明申请
    DYNAMIC ELEMENT MATCHING IN AN INTEGRATED CIRCUIT 审中-公开

    公开(公告)号：US20180356294A1

    公开(公告)日：2018-12-13

    申请号：US15616765

    申请日：2017-06-07

    Applicant: Xilinx, Inc.

    Inventor： Umanath R. Kamath ,  Padraig Kelly ,  John K. Jennings

    IPC: G01K7/01 ,  H03K19/003 ,  H03K19/0175

    CPC classification number: G01K7/01 ,  G01K1/026 ,  G01K7/015 ,  H03K19/00307 ,  H03K19/017581

    Abstract: An example dynamic element matching (DEM) circuit includes: a plurality of bipolar junction transistors (BJTs), each of the plurality of BJTs having a base terminal and a collector terminal coupled to electrical ground; a plurality of pairs of force switches, each pair of force switches coupled to an emitter of a respective one of the plurality of BJTs; a plurality of pairs of sense switches, where each pair of sense switches is coupled to the emitter of a respective one of the plurality of BJTs, a first switch in each pair of sense switches is coupled to a first node, and a second switch in each pair of sense switches is coupled to a second node; a first current source coupled to a first switch in each pair of force switches; and a second current source coupled to a second switch in each pair of force switches.

    Chip tracking with marking database
    304.
    发明授权
    Chip tracking with marking database 有权

    公开(公告)号：US10108925B1

    公开(公告)日：2018-10-23

    申请号：US15204924

    申请日：2016-07-07

    Applicant: Xilinx, Inc.

    Inventor： Craig E. Taylor

    IPC: B07C5/344 ,  G06Q10/08 ,  G06Q30/00 ,  G06F21/31

    Abstract: Techniques for improved semiconductor inventory tracking, control, and testing are provided. The techniques include marking the semiconductor packaging with a 2-dimensional (“2D”) bar code that is stored in a data server. The data server associates the 2D barcode with performance data for the semiconductor, as well as with a “circuit-based identifier,” which comprises hard-wired electrical features that uniquely identify the semiconductor and that are embedded within the semiconductor. Associating the 2D bar code with chip performance reduces the number of times that a chip needs to be tested. Associating the 2D bar code with the circuit-based identifier provides certain functionality such as anti-counterfeiting functionality, device verification, and the like.

    Recalibration of source synchronous systems
    305.
    发明授权
    Recalibration of source synchronous systems 有权

    公开(公告)号：US10103718B1

    公开(公告)日：2018-10-16

    申请号：US15480283

    申请日：2017-04-05

    Applicant: Xilinx, Inc.

    Inventor： Richard W. Swanson ,  Terence J. Magee ,  Qi Zhang ,  Srinivas Vura

    IPC: G11C11/407 ,  G11C7/22 ,  H03K5/134 ,  G11C7/00 ,  G11C7/10 ,  H03K5/06 ,  G11C11/4076 ,  H04L7/00 ,  H03K5/00

    Abstract: An example method of calibrating a source-synchronous system includes: performing initial calibration of a source-synchronous receiver, which is configured to receive data signals and a strobe, to determine an initial strobe delay and initial data delays; setting a strobe delay circuit that delays the strobe to have the initial strobe delay and data delay circuits that delay the data signals to have the initial data delays; measuring first data eye margins of the data signals at a first time; calculating metrics for the data signals based on the first data eye margins; and measuring second data eye margins of the data signals at a second time; and updating the data delay circuits and the strobe delay circuit based on the second data eye margins and the metrics.

    METHODS OF INTERCONNECT FOR HIGH DENSITY 2.5D AND 3D INTEGRATION
    307.
    发明申请
    METHODS OF INTERCONNECT FOR HIGH DENSITY 2.5D AND 3D INTEGRATION 审中-公开

    公开(公告)号：US20180286826A1

    公开(公告)日：2018-10-04

    申请号：US15473294

    申请日：2017-03-29

    Applicant: Xilinx, Inc.

    Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam ,  Henley Liu

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

    Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.

    Error recovery for redundant processing circuits
    309.
    发明授权
    Error recovery for redundant processing circuits 有权

    公开(公告)号：US10078565B1

    公开(公告)日：2018-09-18

    申请号：US15184879

    申请日：2016-06-16

    Applicant: Xilinx, Inc.

    Inventor： Leif Roland Petersson

    IPC: G06F11/00 ,  G06F11/20 ,  G06F11/14

    CPC classification number: G06F11/185 ,  G06F11/1441 ,  G06F11/181

    Abstract: Methods and circuits are disclosed for error recovery in redundant processing systems. Respective instances of a software program are executed in lockstep on redundant processing circuits. Using a control circuit, in response to detecting a non-fatal error, an interrupt is generated and non-functioning ones of the processing circuits are disabled. The interrupt is serviced using the functional processing circuits operating in lockstep. In servicing the interrupt, a processing state of the processing circuits is stored and a reset of the processing circuits is triggered. Following the reset, the processing circuits are configured to operate in lockstep. The state of the processing circuits is restored to the stored processing state and a return from the interrupt is signaled. In response to the signaled return from interrupt, execution of the software program is resumed on the processing circuits in lockstep at a point at which the non-fatal error was detected.

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