公开(公告)号：US10559686B2

公开(公告)日：2020-02-11

申请号：US16018970

申请日：2018-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Hui Zang ,  Steven R. Soss

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/06 ,  H01L29/66 ,  H01L29/08

Abstract: Methods of making a vertical FinFET device having an electrical path over a gate contact landing, and the resulting device including a substrate having a bottom S/D layer thereover and fins extending vertically therefrom; a bottom spacer layer over the bottom S/D layer; a HKMG layer over the bottom spacer layer; a top spacer layer over the HKMG layer; a top S/D layer on top of each fin; top S/D contacts formed over the top S/D layer; an upper ILD layer present in spaces around the top S/D contacts; an isolation dielectric within a portion of a recess of top S/D contacts located above adjacent fins; a gate contact landing within a remaining portion of the recess; a gate contact extending vertically from a bottom surface of the gate contact landing and contacting a portion of the HKMG layer; and an electrical path over at least the gate contact landing.

公开(公告)号：US20190341468A1

公开(公告)日：2019-11-07

申请号：US15971043

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Laertis Economikos ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/3213 ,  H01L21/28

Abstract: A method includes forming a semiconductor device including a plurality of fins formed above a substrate, an isolation structure positioned between the plurality of fins, a plurality of sacrificial gate structures defining gate cavities, and a first dielectric material positioned between the sacrificial gate structures. A gate cut structure is formed in a first gate cavity. A trim etch process is performed to reduce a width of the gate cut structure. Replacement gate structures are formed in the gate cavities after performing the trim etch process. A first replacement gate structure in the first gate cavity is segmented by the gate cut structure.

公开(公告)号：US20190341448A1

公开(公告)日：2019-11-07

申请号：US15968968

申请日：2018-05-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emilie M.S. Bourjot ,  Julien Frougier ,  Yi Qi ,  Ruilong Xie ,  Hui Zang ,  Hsien-Ching Lo ,  Zhenyu Hu

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L21/285 ,  H01L29/66 ,  H01L29/08

Abstract: Various aspects of the disclosure include nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, not just on the top and sides of the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects of the disclosure include nanosheet-FET structures having a bottom isolation to reduce parasitic S/D leakage to the substrate.

公开(公告)号：US10461196B2

公开(公告)日：2019-10-29

申请号：US15662526

申请日：2017-07-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Steven Bentley ,  Ruilong Xie ,  Min Gyu Sung

IPC: H01L29/786 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: Forming a vertical FinFET includes forming a semiconductor fin on a substrate and having a fin mask on an upper surface thereof; laterally recessing the semiconductor fin causing the fin mask; forming a conformal gate liner on the recessed semiconductor fin and the fin mask, wherein the conformal gate liner includes a first portion surrounding the fin mask and a second portion surrounding the recessed fins and being separated from the fin mask by a thickness of the conformal gate liner; forming a gate mask laterally adjacent to the second portion of the conformal gate liner; removing the first portion of the conformal gate liner; removing the gate mask to expose a remaining second portion of the conformal gate liner; and forming a gate contact to the second portion of the conformal gate liner, the remaining second portion of the conformal gate liner defines the gate length.

公开(公告)号：US20190312117A1

公开(公告)日：2019-10-10

申请号：US15949730

申请日：2018-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Hong Yu ,  Yanping Shen ,  Wei Hong ,  Xing Zhang ,  Ruilong Xie ,  Haiting Wang ,  Hui Zhan ,  Yong Jun Shi

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/45 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02

Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.

公开(公告)号：US20190295898A1

公开(公告)日：2019-09-26

申请号：US16403745

申请日：2019-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Daniel Jaeger ,  Chanro Park ,  Laertis Economikos ,  Haiting Wang ,  Hui Zang

IPC: H01L21/8234 ,  H01L21/762 ,  H01L27/088 ,  H01L29/66 ,  H01L21/311

Abstract: Structures and methods of fabricating structures that include contacts coupled with a source/drain region of a field-effect transistor. Source/drain regions are formed adjacent to a temporary gate structure. A sacrificial layer may be disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions, followed by deposition of a fill material, replacement of the temporary gate structure with a functional gate structure, and removal of the fill material. Alternatively, the fill material is formed first and the temporary gate structure is replaced by a functional gate structure; following removal of the fill material, a sacrificial layer is disposed over the source/drain regions and a dielectric pillar is formed in the sacrificial layer between the source/drain regions. A conductive layer having separate portions contacting the separate source/drain regions is formed, with the dielectric pillar separating the portions of the conductive layer.

公开(公告)号：US10424657B2

公开(公告)日：2019-09-24

申请号：US15428312

申请日：2017-02-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andreas Knorr

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/11

Abstract: A tri-gate FinFET device includes a fin that is positioned vertically above and spaced apart from an upper surface of a semiconductor substrate, wherein the fin has an upper surface, a lower surface opposite of the upper surface, a first side surface, and a second side surface opposite of the first side surface. The axis of the fin in a height direction of the fin is oriented substantially parallel to the upper surface of the semiconductor substrate, and the first side surface of the fin contacts an insulating material. A gate structure is positioned around the upper surface, the second side surface, and the lower surface of the fin, and a gate contact structure is conductively coupled to the gate structure.

公开(公告)号：US20190287863A1

公开(公告)日：2019-09-19

申请号：US15920748

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Lars Liebmann ,  Edward J. Nowak ,  Julien Frougier ,  Jia Zeng

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/02

Abstract: Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.

公开(公告)号：US10410929B2

公开(公告)日：2019-09-10

申请号：US15860840

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Jianwei Peng ,  Yi Qi ,  Hsien-Ching Lo ,  Jerome Ciavatti ,  Ruilong Xie

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088 ,  H01L29/66 ,  H01L21/20

Abstract: A method of manufacturing a vertical fin field effect transistor includes forming a first fin in a first device region of a substrate, forming a second fin in a second device region of the substrate, and forming a sacrificial gate having a first gate length adjacent to the first and second fins. After forming a block mask over the sacrificial gate within the first device region, a deposition step or an etching step is used to increase or decrease the gate length of the sacrificial gate within the second device region. Top source/drain junctions formed over the fins are self-aligned to the gate in each of the first and second device regions.

公开(公告)号：US10388770B1

公开(公告)日：2019-08-20

申请号：US15924447

申请日：2018-03-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Christopher M. Prindle

IPC: H01L29/41 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417

Abstract: One illustrative IC product disclosed herein includes a transistor device including a gate structure positioned above an active region, first and second conductive source/drain structures positioned adjacent opposite sidewalls of the gate structure and an insulating material positioned laterally between the gate structure and each of the first and second conductive source/drain structures. The product also includes first and second air gaps positioned adjacent opposite sidewalls of the gate structure, a gate contact structure that is positioned entirely above the active region and conductively coupled to the gate structure and a source/drain contact structure that is positioned entirely above the active region and conductively coupled to at least one of the first and second conductive source/drain structures.