公开(公告)号：US20170293325A1

公开(公告)日：2017-10-12

申请号：US15093584

申请日：2016-04-07

Applicant: Quanta Computer Inc.

Inventor： Chao-Jung CHEN ,  Yaw-Tzorng TSORNG ,  Kun-Pei LIU ,  Yi-Te CHANG

IPC: G06F1/18

CPC classification number: G06F1/18 ,  G06F1/187 ,  G11B33/124 ,  G11B33/128

Abstract: A component carrier with a tray, a slide cage, a level, and a tilting mechanism. The tray has a bottom surface with a groove formed therein. The slide cage is actuatably coupled with the tray and has a receiving space and an undercarriage. The lever is pivotally coupled with the slide cage and has a lower portion for engaging the groove to transition the slide cage between a first position and a second position. The tilting mechanism is coupled with the tray and configured for biasing the slide cage to the second position. In the first position the undercarriage of the slide cage is positioned proximal to the bottom surface of the tray. In the second position a first end portion of the undercarriage of the slide cage is displaced away from the bottom surface and a second end portion is positioned proximal to the bottom surface of the tray.

公开(公告)号：US09763620B2

公开(公告)日：2017-09-19

申请号：US14134653

申请日：2013-12-19

Applicant: Quanta Computer Inc.

Inventor： Chung-Te Li ,  Wen-Chu Yang

IPC: A61B5/00 ,  A61B5/1455 ,  A61B3/14 ,  A61B5/0205 ,  A61B5/021 ,  A61B3/00 ,  G02B27/01 ,  A61B5/024

CPC classification number: A61B5/6803 ,  A61B3/0041 ,  A61B3/14 ,  A61B5/0077 ,  A61B5/02055 ,  A61B5/02108 ,  A61B5/02416 ,  A61B5/14552 ,  G02B27/017 ,  G02B27/0172 ,  G02B27/0176 ,  G02B2027/0112 ,  G02B2027/0134 ,  G02B2027/014 ,  G02B2027/015 ,  G02B2027/0178 ,  G06F19/00

Abstract: A head mounted system includes a physiological signal sensor, a signal processing circuit, a memory, an application processor, and an eyeglass frame. The physiological signal sensor monitors a physiological state to output a physiological signal. The signal processing circuit determines whether the physiological state is abnormal according to the physiological signal. When it is not abnormal, the signal processing circuit controls the physiological signal sensor to monitor the physiological state at a first monitoring frequency. When it is abnormal, the signal processing circuit outputs a warning signal, and controls the physiological signal sensor to monitor the physiological state at a second monitoring frequency greater than the first monitoring frequency. The application processor receives the warning signal and stores physiological data corresponding to the physiological signal in the memory. The eyeglass frame carries the first physiological signal sensor, the signal processing circuit, the memory, and the application processor.

公开(公告)号：US20170265332A1

公开(公告)日：2017-09-14

申请号：US15063901

申请日：2016-03-08

Applicant: Quanta Computer Inc.

Inventor： Chao-Jung CHEN ,  Yi-Chieh CHEN ,  Jen-Mao CHEN ,  Wei-Chun CHANG

IPC: H05K7/20 ,  H05K7/14

CPC classification number: H05K7/20572 ,  G11B33/128 ,  G11B33/142 ,  H05K7/1489 ,  H05K7/20727

Abstract: Systems, methods and computer-readable media for reducing upstream preheat for high-density hard disk drive storage. A system can include first and second rows of storage devices installed in a storage rack, the first and second rows having a first distance between consecutive storage devices. The second row can be located behind the first row and farther away from a source of an airflow than the first row. The system can monitor a temperature associated with the second row and when the temperature rises above a threshold, the system can remove a storage device from the first row. The system can then adjust placement within the first row such that the remaining devices have a second, larger distance between each other to increase airflow to storage devices in the second row and reduce system impedance.

公开(公告)号：USD796569S1

公开(公告)日：2017-09-05

申请号：US29586821

申请日：2016-12-07

Applicant: Quanta Computer Inc.

Designer： Chia-Yuan Chang ,  Ya-Chyi Chou ,  Jung-Wen Chang ,  Kao-Yu Hsu

公开(公告)号：US09748718B2

公开(公告)日：2017-08-29

申请号：US14865969

申请日：2015-09-25

Applicant: Quanta Computer Inc.

Inventor： Kuo-Chun Huang

IPC: H01R12/00 ,  H01R27/02 ,  H01R12/72

CPC classification number: H01R27/02 ,  H01R12/716 ,  H01R12/721 ,  H01R12/724 ,  H01R31/06 ,  H05K1/0215 ,  H05K3/4015 ,  H05K2201/09027 ,  H05K2201/10189 ,  H05K2201/10446

Abstract: A connection adapter is provided. In certain configurations, the connection adapter includes an input portion with a plurality of sets of input connectors, a first output portion extending from the input portion in a first direction and including a first set of output connectors, and a second output portion extending from the input portion in a second direction and including a second set of output connectors. In the connection adapter, the sets of input connectors are electrically coupled to each of the first set of output connectors and the second set of output connectors. Further, the first and second directions are substantially perpendicular to each other, while the input portion extends in a third direction that is not substantially perpendicular to the first direction or the second direction.

公开(公告)号：US20170245399A1

公开(公告)日：2017-08-24

申请号：US15049966

申请日：2016-02-22

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng CHOU ,  Chao-Jung CHEN ,  Tien-Jung CHANG

IPC: H05K7/20

Abstract: Disclosed are a system, method, and computer-readable medium for optimizing a fan control system inside a rack system. In at least one example embodiment, the system can include a rack server with a plurality of chassis each having at least one node, each of the nodes including at least one adjustable air vent and configured for adjusting the at least one adjustable air vent based on an air flow requirement of the node. The system can further include a plurality of fans, where the plurality of fans are configured to operate based on a control signal. The system also can comprise a fan control logic board, wherein the fan control logic board is configured to receive from each node in the plurality of chassis the air flow requirements and based on the plurality of air flow requirements generate and transmit the control signal to the plurality of fans.

公开(公告)号：US20170242758A1

公开(公告)日：2017-08-24

申请号：US15052430

申请日：2016-02-24

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng CHOU ,  Wei-Yu CHIEN

IPC: G06F11/14 ,  G06F9/455 ,  G06F11/22 ,  G06F11/30 ,  G06F1/32

CPC classification number: G06F11/1484 ,  G06F1/3287 ,  G06F9/45558 ,  G06F11/0712 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/2289 ,  G06F11/3062 ,  G06F2009/45587 ,  G06F2201/815 ,  Y02D10/34

Abstract: Systems, methods, and computer-readable storage media for hardware recovery are disclosed. In some examples, a system can detect a hardware error and identify a system component associated with the hardware error. The system can then generate a request configured to trigger an operating system of the system to place the system in a particular operating state. The particular operating state can be determined based on a component type of the system component. The particular operating state can be a first sleep state when the component type is a peripheral component or a second sleep state when the component type is a processor, a memory, or a power supply. The second sleep state can result in a lower power resource consumption than the first sleep state. The system can generate an indication that the system component can be replaced without restarting the operating system.

公开(公告)号：USRE46520E1

公开(公告)日：2017-08-22

申请号：US14686458

申请日：2015-04-14

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih

IPC: G06F1/00 ,  G06F11/00 ,  H04L12/24 ,  H04L12/26 ,  H04L12/56 ,  G06F1/32 ,  G06F11/30 ,  H04L12/12 ,  G06F11/07 ,  H04L12/931

CPC classification number: G06F11/00 ,  G06F1/3209 ,  G06F1/3287 ,  G06F11/0709 ,  G06F11/0793 ,  G06F11/3006 ,  G06F11/3055 ,  H04L12/12 ,  H04L41/00 ,  H04L43/00 ,  H04L49/356 ,  Y02D10/171 ,  Y02D50/40

Abstract: A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node performs an operation system and respectively includes a network port, a network chip and a south bridge chip. The network port is connected to the network switch via a cable. The network chip outputs a power-off signal according to a received power-off packet after the network switch is started. The south bridge chip outputs a shutdown signal to shut down the server node according to the power-off signal when the server node is turned on and the operation system is working normally.

公开(公告)号：US20170214539A1

公开(公告)日：2017-07-27

申请号：US15007804

申请日：2016-01-27

Applicant: Quanta Computer Inc.

Inventor： Wei-Yi CHU ,  Chia-Feng CHENG ,  Chia-Ming LIANG ,  Meng-Huan LU

IPC: H04L12/18 ,  H04L12/26

Abstract: A server system may include a plurality of internal hubs communicatively coupled to a plurality of server nodes. The plurality of internal hubs may communicate with an external hub to transmit broadcast traffic to reach a designated server node. A hub controller, a routing device coupled to the plurality of internal hubs, may select an internal hub from among a plurality of internal hubs based on a link status and a set of hub selection rules. Based on a status of active link and a relative priority of internal hubs, an internal hub is selected as a transmission channel to receive broadcast traffic from the external hub and direct the broadcast traffic to a corresponding server node.

公开(公告)号：US20170212858A1

公开(公告)日：2017-07-27

申请号：US15007753

申请日：2016-01-27

Applicant: Quanta Computer Inc.

Inventor： Wei-Yi CHU ,  Chia-Feng CHENG ,  Kai CHANG ,  Chih-Yu CHEN

IPC: G06F13/40 ,  G06F13/28 ,  G06F12/02 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F12/0246 ,  G06F13/287 ,  G06F13/4282 ,  G06F2212/7208

Abstract: A system for switching between a high performance mode and dual path mode is disclosed. The system includes a first device, a second device, a third device, and a switch configured to receive control signals, and in response causing the switch to selectively couple one or more first lanes of the first device or one or more second lanes of the second device to third lanes of the third device to yield enabled lanes. The system also include a number of the enabled lanes is less than or equal to a number of the third lanes, and the switch is configured to route the enabled lanes associated with the first device to a first portion of the third lanes in an increasing order and to route the enabled lanes associated with the second device to a second portion of the third lanes in a decreasing order.