公开(公告)号：US09755621B1

公开(公告)日：2017-09-05

申请号：US15162827

申请日：2016-05-24

Applicant: STMicroelectronics International N.V.

Inventor： Rohan Sinha ,  Vikas Rana

IPC: H03L5/00 ,  H03K3/356 ,  H03K19/0185

CPC classification number: H03K3/356113 ,  H03K19/018521

Abstract: A level shifting circuit operates at a high voltage level without stressing the transistors. The circuit has the ability to swing between large supply domains. Multiple output voltage levels are supported for the level shifted signal. Additionally, output nodes are stably driven to supply voltage levels that do not vary with respect to process corner and temperature.

公开(公告)号：US09728232B2

公开(公告)日：2017-08-08

申请号：US15167101

申请日：2016-05-27

Applicant: STMicroelectronics International N.V.

Inventor： Amit Chhabra

IPC: G11C5/14 ,  G05F1/46 ,  H03K3/037 ,  H03K5/08 ,  H03K17/22

CPC classification number: G11C5/148 ,  G05F1/46 ,  G05F1/465 ,  H03K3/0377 ,  H03K5/082 ,  H03K17/223

Abstract: When powering-up or exiting from a sleep mode, the ramping up of various supply voltage nodes may occur at different rates. Thus, in a dual-rail memory circuit, a first voltage rail may be at voltage before a second voltage rail. Such a transient state of operation may lead to current spikes that unnecessarily draw power and introduce undesired inefficiency. An internal sleep signal generation circuit in the dual-rail memory circuit precisely controls an internal sleep signal such that the transition from off or sleep mode to operating mode is set to assure that the supply voltage nodes are close enough to the at-voltage operating level before releasing the sleep mode.

公开(公告)号：US09705520B1

公开(公告)日：2017-07-11

申请号：US15380246

申请日：2016-12-15

Applicant: STMicroelectronics International N.V.

Inventor： Ashish Kumar ,  Chandrajit Debnath ,  Pratap Narayan Singh

IPC: H03M1/38 ,  H03M1/06 ,  H03M1/12 ,  H03M1/10

CPC classification number: H03M1/466 ,  H03M1/0863 ,  H03M1/1009 ,  H03M1/124 ,  H03M1/1245 ,  H03M1/164 ,  H03M1/38 ,  H03M1/44

Abstract: An embodiment circuit includes a first reference source configured to provide a first reference signal to an analog-to-digital convertor (ADC). The circuit also includes a filter coupled to an output of the first reference source and configured to filter the first reference signal to produce a filtered first reference signal. The circuit further includes a second reference source coupled to an output of the filter. The second reference source is configured to provide a second reference signal to the ADC, and the second reference signal is generated based on the filtered first reference signal.

公开(公告)号：US09698771B1

公开(公告)日：2017-07-04

申请号：US15203461

申请日：2016-07-06

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: H03K17/22 ,  H03K5/19 ,  H03K19/20

CPC classification number: H03K17/223 ,  G01R31/2832 ,  G06F1/24 ,  G06F1/30 ,  H03K5/19 ,  H03K17/22 ,  H03K19/20

Abstract: A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.

公开(公告)号：US09696351B2

公开(公告)日：2017-07-04

申请号：US14585357

申请日：2014-12-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Daljeet Kumar ,  Tapas Nandy ,  Surendra Kumar

IPC: G01R19/04 ,  G01R19/25

CPC classification number: G01R19/04 ,  G01R19/2503

Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.

公开(公告)号：US09685867B2

公开(公告)日：2017-06-20

申请号：US14466666

申请日：2014-08-22

Applicant: STMicroelectronics International N.V.

Inventor： Bohumil Janik

IPC: H02M3/158

CPC classification number: H02M3/1582

Abstract: A method supplies power from a power source to a load. The method includes, in a first mode, electrically coupling a step-down converter node of a step-down converter alternately to the power source via a conductive bypass path that bypasses a step-up converter and to ground. The step-up converter has an input electrically coupled to the power source and the step-down converter has an output electrically coupled to the load. The method further includes, in a second mode, coupling the step-down converter node alternately to the power source via the bypass path and to an output of the step-up converter.

公开(公告)号：US09654252B2

公开(公告)日：2017-05-16

申请号：US14931331

申请日：2015-11-03

Applicant: STMicroelectronics International N.V.

Inventor： Achraf Dhayni ,  Hussein Hijazi

IPC: H04B7/04 ,  H04L1/06 ,  H04L1/00 ,  H04L25/03 ,  H04B7/0413

CPC classification number: H04L1/0054 ,  H04B7/0413 ,  H04L1/0631 ,  H04L25/03197 ,  H04L25/03242 ,  H04L25/03961 ,  H04L2025/03414 ,  H04L2025/0342 ,  H04L2025/03426

Abstract: A receiver estimates a vector of emitted symbols over a MIMO transmission channel which is emitted by emitting antennas. The receiver receives a vector of received symbols on receiving antennas. Estimation of the vector of emitted symbols is made by calculating a metric associated with a criterion for each vector of a subset of all possible vectors of emitted symbols and selecting an estimation for said vector of emitted symbols as the vector of emitted symbols among said subset which minimizes said metric.

公开(公告)号：US09621031B1

公开(公告)日：2017-04-11

申请号：US14923776

申请日：2015-10-27

Applicant: STMicroelectronics International N.V.

Inventor： Jitendra Jain ,  Ranajay Mallik

IPC: H05B37/04 ,  H02M3/04 ,  H05B33/08

CPC classification number: H02M3/04 ,  H05B33/0815 ,  H05B33/0827 ,  H05B33/0845 ,  H05B33/0887 ,  Y02B20/347

Abstract: A tunable voltage regulator has an output generating a variable voltage and an input that receives a trimming signal for controlling the output variable voltage. A current regulating circuit operates to regulate a current flowing through a load in response to the variable voltage. A control circuit senses the variable voltage and a drop voltage of the current regulating circuit, and determines whether the current regulating circuit has failed to regulate the current flowing through the load because the variable voltage is too low. In response thereto, the control circuit generates the trimming signal to set the variable voltage to a value sufficient for the current regulating circuit to successfully regulate the current flowing through the load.

公开(公告)号：US20170064321A1

公开(公告)日：2017-03-02

申请号：US14837051

申请日：2015-08-27

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vindhyeshwari Kumar KASHYAP ,  Ajit Singh MOTRA ,  Mahesh Narain SHUKLA ,  Tarun SINGAL

IPC: H04N19/44 ,  H04N19/85 ,  H04N19/423 ,  H04N19/436

CPC classification number: H04N19/436 ,  H04N19/91

Abstract: A video decoder includes an input configured to receive a plurality of bins of a video digital data stream to be decoded. A processor and a memory associated therewith are configured to perform parallel decoding of multiple bins of the plurality of bins in a given processing cycle based upon a table containing delta range values and probable symbols.

Abstract translation: 视频解码器包括被配置为接收待解码的视频数字数据流的多个存储槽的输入。 处理器和与其相关联的存储器被配置为基于包含增量范围值和可能符号的表，在给定处理周期内执行多个箱中的多个箱的并行解码。

公开(公告)号：US09559665B2

公开(公告)日：2017-01-31

申请号：US14788714

申请日：2015-06-30

Applicant: STMicroelectronics International N.V.

Inventor： Amit Chhabra

IPC: H03K3/011 ,  G11C11/417 ,  H03K17/687 ,  H01L27/11

CPC classification number: H03K3/011 ,  G01K3/005 ,  G01K7/01 ,  G11C5/146 ,  G11C7/04 ,  G11C11/417 ,  H01L27/1104 ,  H03K17/687

Abstract: An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A threshold detector selectively applies either a first voltage or second voltage to the doped well region based on whether the temperature of the semiconductor substrate is above or below a threshold temperature.

Abstract translation: 集成电路管芯包括形成在半导体衬底中的多个晶体管，在半导体衬底的掺杂阱区域上的晶体管的体区。 阈值检测器基于半导体衬底的温度是高于还是低于阈值温度来选择性地将第一电压或第二电压施加到掺杂阱区。