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公开(公告)号：US10263761B2
公开(公告)日：2019-04-16
申请号：US16032616
申请日：2018-07-11
Applicant: Rambus Inc.
Inventor： Masum Hossain , Brian Leibowitz , Jihong Ren
Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.
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公开(公告)号：US10262750B2
公开(公告)日：2019-04-16
申请号：US15393634
申请日：2016-12-29
Applicant: RAMBUS INC.
Inventor： Thomas Vogelsang , William Ng , Frederick A. Ware
Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.
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公开(公告)号：US20190108101A1
公开(公告)日：2019-04-11
申请号：US16156953
申请日：2018-10-10
Applicant: Rambus Inc.
Inventor： Shih-ho WU , Christopher HAYWOOD
Abstract: The present invention is directed to computer storage systems and methods thereof. More specifically, embodiments of the present invention provide an isolated storage control system that includes both a non-volatile memory and a volatile memory. The non-volatile memory comprises a data area and a metadata area. In power failure or similar situations, content of the volatile memory is copied to the data area of the non-volatile memory, and various system parameters are stored at the metadata area. When the system restores its operation, the information at the metadata area is processed, and the content stored at the data area of the non-volatile memory is copied to the volatile memory. There are other embodiments as well.
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公开(公告)号：US20190102318A1
公开(公告)日：2019-04-04
申请号：US16149553
申请日：2018-10-02
Applicant: Rambus Inc.
Inventor： Hongzhong Zheng , Trung A. Diep
IPC: G06F12/1045 , G06F12/0802 , G06F12/1009
Abstract: The disclosed embodiments relate to a computer system with a cache memory that supports tagless addressing. During operation, the system receives a request to perform a memory access, wherein the request includes a virtual address. In response to the request, the system performs an address-translation operation, which translates the virtual address into both a physical address and a cache address. Next, the system uses the physical address to access one or more levels of physically addressed cache memory, wherein accessing a given level of physically addressed cache memory involves performing a tag-checking operation based on the physical address. If the access to the one or more levels of physically addressed cache memory fails to hit on a cache line for the memory access, the system uses the cache address to directly index a cache memory, wherein directly indexing the cache memory does not involve performing a tag-checking operation and eliminates the tag storage overhead.
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公开(公告)号：US10248358B2
公开(公告)日：2019-04-02
申请号：US15990211
申请日：2018-05-25
Applicant: RAMBUS INC.
Inventor： Frederick A. Ware , Thomas Vogelsang
Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.
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Patent Agency Ranking
公开(公告)号：US10248342B2
公开(公告)日：2019-04-02
申请号：US16145931
申请日：2018-09-28
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Robert E. Palmer , John W. Poulton
Abstract: A system includes a memory controller and a memory device having a command interface and a plurality of memory banks, each with a plurality of rows of memory cells. The memory controller transmits an auto-refresh command to the memory device. Responsive to the auto-refresh command, during a first time interval, the memory device performs refresh operations to refresh the memory cells and the command interface of the memory device is placed into a calibration mode for the duration of the first time interval. Concurrently, during at least a portion of the first time interval, the memory controller performs a calibration of the command interface of the memory device. The auto-refresh command may specify an order in which memory banks of the memory device are to be refreshed, such that the memory device sequentially refreshes a respective row in the plurality of memory banks in the specified bank order.
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公开(公告)号：US20190095264A1
公开(公告)日：2019-03-28
申请号：US16120819
申请日：2018-09-04
Applicant: Rambus Inc.
Inventor： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC: G06F11/07 , G06F11/00 , G06F11/10 , H04L1/00 , G06F3/06 , H04L1/08 , H04L1/18 , G11C29/52 , G06F11/14 , H03M13/03 , G06F11/20
Abstract: A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
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公开(公告)号：US10236051B2
公开(公告)日：2019-03-19
申请号：US15666496
申请日：2017-08-01
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC: G11C11/24 , G11C11/4076 , G11C7/10 , G06F13/16 , G06F13/40 , G11C5/06 , G11C29/02 , G11C29/50 , G11C8/18 , G11C7/22 , G06F1/10 , G11C11/409 , G11C11/4096 , G06F1/06 , G06F1/12 , G06F3/06 , G11C7/04
Abstract: A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the write data to be sampled by the DRAM using a timing signal. The adjusting circuitry adjusts transmit timing of the write data and of the timing signal such that an edge transition of the timing signal is aligned with an edge transition of the clock signal at the DRAM.
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329.发明授权公开(公告)号：US10235242B2
公开(公告)日：2019-03-19
申请号：US15260880
申请日：2016-09-09
Applicant: Rambus Inc.
Inventor： Kenneth L. Wright , Frederick A. Ware
Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. The memory components can be configured to route data around defective data connections to maintain full capacity and continue to support memory transactions.
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公开(公告)号：US20190075000A1
公开(公告)日：2019-03-07
申请号：US16057604
申请日：2018-08-07
Applicant: Rambus Inc.
Inventor： Brian S. Leibowitz , Hae-Chang Lee , Jihong Ren , Ruwan Ratnayake
Abstract: A method is disclosed. The method includes sampling a data signal having a voltage value at an expected edge time of the data signal. A first alpha value is generated, and a second alpha value generated in dependence upon the voltage value. The data signal is adjusted by the first alpha value to derive a first adjusted signal. The data signal is adjusted by the second alpha value to derive a second adjusted signal. The first adjusted signal is sampled to output a first data value while the second adjusted signal is sampled to output a second data value. A selection is made between the first data value and the second data value as a function of a prior received data value to determine a received data value.
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