公开(公告)号：US20200004290A1

公开(公告)日：2020-01-02

申请号：US16567479

申请日：2019-09-11

Applicant: Intel Corporation

Inventor： Nadine L. Dabby ,  Sasha N. Oster ,  Aleksandar Aleksov ,  Braxton Lathrop ,  Racquel L. Fygenson

IPC: G06F1/16

Abstract: Systems and methods describe herein provide a solution to the technical problem of creating a wearable electronic devices. In particular, these systems and methods enable electrical and mechanical attachment of stretchable or flexible electronics to fabric. A stretchable or flexible electronic platform is bonded to fabric using a double-sided fabric adhesive, and conductive adhesive is used to join pads on the electronic platform to corresponding electrical leads on the fabric. An additional waterproofing material may be used over and beneath the electronic platform to provide a water-resistant or waterproof device This stretchable or flexible electronic platform integration process allows the platform to bend and move with the fabric while protecting the conductive connections. By using flexible and stretchable conductive leads and adhesives, the platform is more flexible and stretchable than traditional rigid electronics enclosures.

公开(公告)号：US20190355636A1

公开(公告)日：2019-11-21

申请号：US16526497

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Mihir K. Roy ,  Aleksandar Aleksov ,  Yidnekachew S. Mekonnen ,  Javier Soto Gonzalez ,  Feras Eid ,  Suddhasattwa Nad ,  Meizi Jiao

IPC: H01L23/12 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US10475736B2

公开(公告)日：2019-11-12

申请号：US15718012

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Arnab Sarkar ,  Arghya Sain ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prashant D. Parmar ,  Sujit Sharan ,  Johanna M. Swan ,  Feras Eid

IPC: H01L23/50 ,  H01L21/48 ,  H01L23/498 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

公开(公告)号：US10410939B2

公开(公告)日：2019-09-10

申请号：US15776755

申请日：2015-12-16

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Mihir K. Roy ,  Aleksandar Aleksov ,  Yidnekachew S. Mekonnen ,  Javier Soto Gonzalez ,  Feras Eid ,  Suddhasattwa Nad ,  Meizi Jiao

IPC: H01L23/52 ,  H01L23/12 ,  H01L23/48 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US20190198965A1

公开(公告)日：2019-06-27

申请号：US16325522

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios C. Dogiamis ,  Sasha N. Oster ,  Adel A. Elsherbini ,  Brandon M. Rawlings ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Richard J. Dischler ,  Johanna M. Swan

IPC: H01P11/00 ,  H01P3/12

CPC classification number: H01P11/002 ,  H01P3/122

Abstract: An apparatus comprises a waveguide section including an outer layer of conductive material tubular in shape and having multiple ends; and a joining feature on at least one of the ends of the waveguide section configured for joining to a second separate waveguide section.

公开(公告)号：US20190173149A1

公开(公告)日：2019-06-06

申请号：US16325301

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Sasha N. Oster ,  Georgios C. Dogiamis ,  Telesphor Kamgaing ,  Shawna M. Liff ,  Aleksandar Aleksov ,  Johanna M. Swan ,  Brandon M. Rawlings ,  Richard J. Dischler

IPC: H01P3/12 ,  H01P11/00 ,  H01P3/127 ,  H01P3/16

Abstract: An apparatus comprises a waveguide including: an elongate waveguide core including a dielectric material, wherein the waveguide core includes at least one space arranged lengthwise along the waveguide core that is void of the dielectric material; and a conductive layer arranged around the waveguide core.

公开(公告)号：US10263312B2

公开(公告)日：2019-04-16

申请号：US15282050

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Sasha N. Oster ,  Aleksandar Aleksov ,  Georgios C. Dogiamis ,  Telesphor Kamgaing ,  Adel A. Elsherbini ,  Shawna M. Liff ,  Johanna M. Swan ,  Brandon M. Rawlings ,  Richard J. Dischler

IPC: H01P3/12 ,  H01P3/16 ,  H01P11/00 ,  H01P3/14

Abstract: A method of making a waveguide ribbon that includes a plurality of waveguides comprises joining a first sheet of dielectric material to a first conductive sheet of conductive material, patterning the first sheet of dielectric material to form a plurality of dielectric waveguide cores on the first conductive sheet, and coating the dielectric waveguide cores with substantially the same conductive material as the conductive sheet to form the plurality of waveguides.

公开(公告)号：US10204855B2

公开(公告)日：2019-02-12

申请号：US14653033

申请日：2014-07-11

Applicant: Intel Corporation

Inventor： Alejandro Levander ,  Tatyana Andryushchenko ,  David Staines ,  Mauro Kobrinsky ,  Aleksandar Aleksov ,  Dilan Seneviratne ,  Javier Soto Gonzalez ,  Srinivas Pietambaram ,  Rafiqul Islam

IPC: H01L23/00 ,  H01L23/498 ,  B23B5/16 ,  B32B27/08 ,  B32B27/28 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/31 ,  H01L25/00 ,  H05K1/02

Abstract: Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.

公开(公告)号：US10080290B2

公开(公告)日：2018-09-18

申请号：US14943234

申请日：2015-11-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Srinivas Pietambaram ,  Rahul N. Manepalli

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K1/184 ,  H01L2224/04105 ,  H01L2924/18162 ,  H05K1/0283 ,  H05K1/0298 ,  H05K1/113 ,  H05K1/185 ,  H05K3/007 ,  H05K3/4697 ,  H05K2201/0133 ,  H05K2201/09263 ,  H05K2203/0191 ,  H05K2203/1469

Abstract: An embedded electronic package includes a stretchable body that includes at least one electronic component, wherein each electronic component includes a back side that is exposed from the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components. In some forms, the embedded electronic package includes a stretchable body that includes an upper surface and a lower surface, wherein the stretchable body includes at least one electronic component, wherein each electronic component is fully embedded in the stretchable body and the same distance from the upper surface of the stretchable body; and a plurality of meandering conductors that are electrically connected to one or more of the electronic components.

公开(公告)号：US10039186B2

公开(公告)日：2018-07-31

申请号：US15267872

申请日：2016-09-16

Applicant: Intel Corporation

Inventor： Amit Sudhir Baxi ,  Vincent S. Mageshkumar ,  Adel A. Elsherbini ,  Sasha Oster ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H05K1/00 ,  H05K1/14 ,  H05K1/18 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/147 ,  A61B5/00 ,  A61B5/6833 ,  A61B2562/164 ,  A61B2562/166 ,  H05K1/0283 ,  H05K1/112 ,  H05K1/181 ,  H05K3/365 ,  H05K2201/10151 ,  H05K2201/10265 ,  H05K2201/10303 ,  H05K2201/10318

Abstract: A circuit interconnect may be used in biometric data sensing and feedback applications. A circuit interconnect may be used in device device-to-device connections (e.g., Internet of Things (IoT) devices), including applications that require connection between stretchable and rigid substrates. A circuit interconnect may include a multi-pin, snap-fit attachment mechanism, where the attachment mechanism provides an electrical interconnection between a rigid substrate and a flexible or stretchable substrate. The combination of a circuit interconnect and flexible or stretchable substrate provides improved electrical connection reliability, allows for greater stretchability and flexibility of the circuit traces, and allows for more options in connecting a stretchable circuit trace to a rigid PCB.