公开(公告)号：US06787852B1

公开(公告)日：2004-09-07

申请号：US10278420

申请日：2002-10-23

Applicant: Bin Yu ,  Ralf van Bentum

Inventor： Bin Yu ,  Ralf van Bentum

IPC: H01L2701

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78684

Abstract: A semiconductor-on-insulator (SOI) device. The SOI device includes a substrate having a buried oxide layer disposed thereon and an active layer disposed on the buried oxide layer. The active layer has an active region defined by isolation regions, the active region having a source and a drain with a body disposed therebetween. The source and the drain have a selectively grown silicon-germanium region disposed under an upper layer of selectively grown silicon. The silicon-geranium regions form heterojunction portions respectively along the source/body junction and the drain/body junction.

Abstract translation: 绝缘体上半导体（SOI）器件。 SOI器件包括其上设置有掩埋氧化物层的衬底和设置在掩埋氧化物层上的有源层。 有源层具有由隔离区域限定的有源区域，有源区域具有源极和漏极，其间设置有主体。 源极和漏极具有选择性地生长的硅 - 锗区域，其设置在选择性生长的硅的上层下方。 硅锗天线分别沿着源极/主体结和漏极/主体结形成异质结部分。

公开(公告)号：US06784101B1

公开(公告)日：2004-08-31

申请号：US10146029

申请日：2002-05-16

Applicant: Bin Yu ,  David Wu

Inventor： Bin Yu ,  David Wu

IPC: H01L2144

CPC classification number: H01L21/022 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/28194 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/1054 ,  H01L29/517

Abstract: A semiconductor device is formed by providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice therein, forming a thin buffer/interfacial layer of a low-k dielectric material on the upper surface of the semiconductor substrate, and forming a layer of a high-k dielectric material on the thin buffer/interfacial layer of a low-k dielectric material. Embodiments include forming the thin buffer/interfacial layer and high-k layer at a minimum temperature sufficient to effect formation of the respective dielectric layer without incurring, or at least minimizing, strain relaxation of the strained lattice semiconductor layer.

Abstract translation: 半导体器件通过在其上表面设置包含应变晶格半导体层并在其中具有预选量的晶格的半导体衬底形成，在上表面上形成低k介电材料的薄缓冲/界面层 并且在低k电介质材料的薄缓冲层/界面层上形成高k电介质材料层。 实施例包括在足以实现相应电介质层的形成的最小温度下形成薄缓冲层/界面层和高k层，而不会引起应变晶格半导体层的应变弛豫或至少最小化应变弛豫。

公开(公告)号：US06774436B1

公开(公告)日：2004-08-10

申请号：US09900400

申请日：2001-07-05

Applicant: Bin Yu ,  Ralf van Bentum

Inventor： Bin Yu ,  Ralf van Bentum

IPC: H01L310392

CPC classification number: H01L29/66772 ,  H01L29/78612 ,  H01L29/78624

Abstract: A semiconductor-on-insulator (SOI) device. The SOi device includes a substrate, an insulator layer disposed on the substrate and an active region disposed on the insulator layer. The active region includes a source, a drain, and a body disposed therebetween. The source and body form an abrupt or hyperabrupt source/body junction. A gate is disposed on the body to operatively form a transistor. An implanted region forms an interface between the body and the drain, the implanted region formed by tilted atom implantation in a direction towards the active region and under the gate from an angle tilted towards the drain with respect to vertical, the implanted region resulting in the formation of a graded drain/body junction. Also disclosed is a method of fabricating the SOI device.

Abstract translation: 绝缘体上半导体（SOI）器件。 SOi器件包括衬底，设置在衬底上的绝缘体层和设置在绝缘体层上的有源区。 有源区域包括源极，漏极和设置在它们之间的主体。 来源和身体形成突然或超破坏的源/体结。 栅极设置在主体上以可操作地形成晶体管。 植入区域在主体和漏极之间形成界面，通过倾斜的原子注入在朝向有源区域的方向上形成的注入区域和从栅极相对于垂直方向朝向漏极倾斜的角度形成注入区域， 形成分级排水/身体结。 还公开了一种制造SOI器件的方法。

公开(公告)号：US06746944B1

公开(公告)日：2004-06-08

申请号：US10341345

申请日：2003-01-14

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L213205

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/7833

Abstract: Semiconductor devices with reduced NiSi/Si interface contact resistance are fabricated by forming preamorphized regions in a substrate at a depth overlapping the subsequently formed NiSi/Si interface, ion implanting impurities to form deep source/drain implants overlapping the preamorphized regions deeper in the substrate and laser thermal annealing to activate the deep source/drain regions. Nickel silicide layers are then formed in a main surface of the substrate and on the gate electrode. Embodiments include forming deep source/drain regions with an activated impurity concentration of 1×1020 to 1×1021 atoms/cm3 at the NiSi/Si interface.

Abstract translation: 具有降低的NiSi / Si界面接触电阻的半导体器件通过在与随后形成的NiSi / Si界面重叠的深度的衬底中形成预变形区域，离子注入杂质以形成与衬底中较深的预变形区域重叠的深源/漏注入; 激光热退火激活深源/漏区。 然后在衬底的主表面和栅电极上形成硅化镍层。 实施例包括在NiSi / Si界面处形成具有1×10 20至1×10 21原子/ cm 3的活化杂质浓度的深源/漏区。

公开(公告)号：US06709935B1

公开(公告)日：2004-03-23

申请号：US09817580

申请日：2001-03-26

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/66477 ,  H01L21/26506 ,  H01L29/1054 ,  H01L29/66545

Abstract: A method of forming a specialized channel region removes a sacrificial gate material and provides a semiconductor implant though the recess associated with the remove sacrificial gate material. The process can be utilized to form a silicon germanium layer in the channel region having a sharp profile in the vertical direction. Further, the silicon germanium layer can be ultra-thin. The silicon germanium channel region has increased charge mobility with respect to conventional channel regions.

Abstract translation: 形成专用沟道区的方法去除牺牲栅极材料并通过与去除的牺牲栅极材料相关联的凹槽来提供半导体注入。 该方法可用于在垂直方向具有锐利轮廓的通道区域中形成硅锗层。 此外，硅锗层可以是超薄的。 硅锗沟道区相对于常规沟道区具有增加的电荷迁移率。

公开(公告)号：US06703281B1

公开(公告)日：2004-03-09

申请号：US10274038

申请日：2002-10-21

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L29/6653 ,  H01L21/26506 ,  H01L21/268 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6659

Abstract: MOSFETs are fabricated with accurately defined, high and uniformly concentrated source/drain regions and extensions employing plural, sequential pre-amorphizing, implanting and laser thermal annealing steps with intervening spacer removal. Embodiments include forming sidewall spacers on a gate electrode, sequentially pre-amorphizing, ion implanting and laser thermal annealing to form deep source/drain regions, removing the sidewall spacers, and then sequentially pre-amorphizing, ion implanting and laser thermal annealing to form shallow source/drain extensions.

Abstract translation: 使用精确定义的高均匀浓度的源极/漏极区域和采用多个连续的前非晶化，注入和激光热退火步骤的间隔来制造MOSFET，并且间隔物移除。 实施例包括在栅电极上形成侧壁间隔物，顺序地预非晶化，离子注入和激光热退火以形成深源极/漏极区域，去除侧壁间隔物，然后依次预非晶化，离子注入和激光热退火以形成浅的 源/漏扩展。

公开(公告)号：US06696725B1

公开(公告)日：2004-02-24

申请号：US09527227

申请日：2000-03-16

Applicant: Judy X. An ,  Bin Yu

Inventor： Judy X. An ,  Bin Yu

IPC: H01L31119

CPC classification number: H01L29/66484 ,  H01L21/28105 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/7831

Abstract: A semiconductor device with reduced hot carrier injection and punch through is formed with a dual gate electrode comprising edge conductive portions, a central conductive portion, and dielectric sidewall spacers formed between the edge conductive portions and central conductive portion. The edge conductive portions provide high potential barriers against the active regions, thereby reducing threshold voltage roll off and leakage current.

Abstract translation: 具有减少的热载流子注入和穿通的半导体器件由双栅极电极形成，该双栅电极包括边缘导电部分，中心导电部分和形成在边缘导电部分和中心导电部分之间的电介质侧壁间隔物。 边缘导电部分提供抵抗有源区域的高电势势垒，从而降低阈值电压滚降和漏电流。

公开(公告)号：US06682973B1

公开(公告)日：2004-01-27

申请号：US10147650

申请日：2002-05-16

Applicant: Eric N. Paton ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Qi Xiang ,  Bin Yu

IPC: H01L218242

CPC classification number: H01L21/28185 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02247 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28291 ,  H01L21/31604 ,  H01L21/31662 ,  H01L21/31691 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: A process for fabricating a semiconductor device having a high-K dielectric layer over a silicon substrate, including steps of growing on the silicon substrate an interfacial layer of a silicon-containing dielectric material; and depositing on the interfacial layer a layer comprising at least one high-K dielectric material, in which the interfacial layer is grown by laser excitation of the silicon substrate in the presence of oxygen, nitrous oxide, nitric oxide, ammonia or a mixture of two or more thereof. In one embodiment, the silicon-containing material is silicon dioxide, silicon nitride, silicon oxynitride or a mixture thereof.

Abstract translation: 一种用于制造在硅衬底上具有高K电介质层的半导体器件的方法，包括在硅衬底上生长含硅介电材料的界面层的步骤; 并且在所述界面层上沉积包含至少一种高K电介质材料的层，其中所述界面层通过在氧，一氧化二氮，一氧化氮，氨或两者的混合物的存在下通过硅衬底的激光激发而生长 或更多。 在一个实施方案中，含硅材料是二氧化硅，氮化硅，氮氧化硅或其混合物。

公开(公告)号：US06670260B1

公开(公告)日：2003-12-30

申请号：US09577332

申请日：2000-05-24

Applicant: Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

Inventor： Bin Yu ,  Ming-Ren Lin ,  Shekhar Pramanick

IPC: H01L21425

CPC classification number: H01L29/6659 ,  H01L29/0649 ,  H01L29/78

Abstract: A thin filmed fully-depleted silicon-on-insulator (SOI) metal oxide semiconductor field defect transistor (MOSFET) utilizes a local insulation structure. The local insulative structure includes a buried silicon dioxide region under the channel region. The MOSFET body thickness is very small and yet silicon available outside of the channel region and buried silicon dioxide region is available for sufficient depths of silicide in the source and drain regions. The buried silicon dioxide region can be formed by a trench isolation technique or a LOCOS technique.

Abstract translation: 薄膜完全耗尽的绝缘体上硅（SOI）金属氧化物半导体场缺陷晶体管（MOSFET）利用局部绝缘结构。 局部绝缘结构包括沟道区下方的埋置二氧化硅区域。 MOSFET体的厚度非常小，而在沟道区域和掩埋的二氧化硅区域之外可用的硅可用于源极和漏极区域中足够的硅化物深度。 掩埋的二氧化硅区域可以通过沟槽隔离技术或LOCOS技术形成。

公开(公告)号：US06630386B1

公开(公告)日：2003-10-07

申请号：US09618857

申请日：2000-07-18

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21336

CPC classification number: H01L21/26506 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/324 ,  H01L29/1083 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659

Abstract: A method of manufacturing an integrated circuit may include the steps of annealing a gate structure and a halo section disposed over a substrate using a first temperature, implanting dopants to form drain and source regions, and annealing drain and source regions at a second temperature. The second temperature is substantially less than the first temperature.

Abstract translation: 制造集成电路的方法可以包括以下步骤：使用第一温度退火设置在衬底上的栅极结构和卤素区段，注入掺杂剂以形成漏极和源极区域，以及在第二温度下退火漏极和源极区域。 第二温度基本上小于第一温度。