公开(公告)号：US09001882B2

公开(公告)日：2015-04-07

申请号：US13165015

申请日：2011-06-21

Applicant: Ravin Sachdeva ,  Sumit Johar ,  Daniele Alfonso

Inventor： Ravin Sachdeva ,  Sumit Johar ,  Daniele Alfonso

IPC: H04B1/66 ,  H04N19/42 ,  H04N19/91

CPC classification number: H04N19/42 ,  H04N19/91

Abstract: An embodiment relates to a decoder for decoding CABAC encoded video data in real time for HDTV applications. The decoder comprises a binary arithmetic decoder block for converting an input bit stream into a bin string, a context memory for storing a plurality of context values, and a plurality of finite state machines. Each of the finite state machines is adapted for decoding a particular one of the H.264 syntax elements by providing the binary arithmetic decoder block with an index of the relevant context value within the context memory and by converting the resulting bin stream into a value of the current syntax element. In this manner, a performance of one bin per cycle may be achieved.

Abstract translation: 实施例涉及用于HDTV应用实时解码CABAC编码视频数据的解码器。 解码器包括用于将输入比特流转换成bin字符串的二进制算术解码器块，用于存储多个上下文值的上下文存储器以及多个有限状态机。 每个有限状态机适于通过向二进制算术解码器块提供上下文存储器内的相关上下文值的索引来解码H.264语法元素中的特定一个，并且通过将所得到的bin流转换为 当前语法元素。 以这种方式，可以实现每个循环一个箱的性能。

公开(公告)号：US08994416B2

公开(公告)日：2015-03-31

申请号：US14045642

申请日：2013-10-03

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Chittoor Parthasarathy ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

IPC: H03B19/00 ,  H03K3/02 ,  H03K3/037

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 该应用提出了一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

公开(公告)号：US20150084609A1

公开(公告)日：2015-03-26

申请号：US14492877

申请日：2014-09-22

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Alexandre Pons ,  Karel Napravnik

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: A circuit may include a differential amplifier and a feedback network. The feedback network may have a chain of resistance sets coupled in series, with a first end terminal coupled to an output terminal of the differential amplifier and a second end terminal coupled to a power reference terminal of the differential amplifier. Respective nodes may be coupled between successive ones of the resistance sets. A feedback terminal may be coupled to an inverting input terminal of the differential amplifier. A controller may control a set of switches to electrically couple a given node to the feedback terminal. A first resistance set of the chain adjacent the first end terminal may be two resistance subsets coupled in series, with an intermediate node coupled therebetween. A programmable current generator may have a current output coupled to the intermediate node and may produce a controlled current flowing at the current output terminal.

Abstract translation: 电路可以包括差分放大器和反馈网络。 反馈网络可以具有串联耦合的电阻组，其中第一端子耦合到差分放大器的输出端子，以及耦合到差分放大器的功率参考端子的第二端子端子。 相应的节点可以在连续的电阻集合中耦合。 反馈端子可以耦合到差分放大器的反相输入端子。 控制器可以控制一组开关以将给定节点电耦合到反馈端子。 邻近第一端子的链的第一电阻组可以是串联耦合的两个电阻子集，其间连接有中间节点。 可编程电流发生器可以具有耦合到中间节点的电流输出并且可以产生在当前输出端子处流动的受控电流。

公开(公告)号：US20150077165A1

公开(公告)日：2015-03-19

申请号：US14485887

申请日：2014-09-15

Applicant: STMicroelectronics International N.V.

Inventor： Didier Harnay ,  Stephane Pineau ,  Francois Sittler

IPC: H03L7/107 ,  H03L7/08

CPC classification number: H03L7/1075 ,  H03L7/0802 ,  H04B15/04

Abstract: A method is for rejecting spurs within a chip containing analog and digital functions. The spurs may be timed by a clock signal derived from the output frequency of a high frequency phase locked loop. Original analog rejection bandwidths associated with operation of analog functions may be determined, and then original spurs associated with operation of the digital functions and capable of directly or indirectly affecting the original analog rejection bandwidths may be identified. A final analog rejection bandwidth may be determined based on the original analog rejection bandwidths, and final spurs may be obtained based on the original spurs. A frequency shift of the output frequency of the high frequency phase locked loop to effectuate a rejection of the final spurs from the final analog rejection bandwidth may be determined, and the high frequency phase locked loop may be controlled to shift the output frequency by the frequency shift.

Abstract translation: 一种方法是在包含模拟和数字功能的芯片中拒绝杂散。 杂散可以由从高频锁相环的输出频率导出的时钟信号定时。 可以确定与模拟功能的操作相关联的原始模拟拒绝带宽，然后可以识别与数字功能的操作相关联并能够直接或间接影响原始模拟拒绝带宽的原始杂散。 可以基于原始模拟拒绝带宽来确定最终的模拟拒绝带宽，并且可以基于原始杂散获得最终的杂散。 可以确定高频锁相环的输出频率的频移以实现最终模拟抑制带宽的最终杂散的抑制，并且可以控制高频锁相环以将输出频率移位频率 转移。

公开(公告)号：US20150029795A1

公开(公告)日：2015-01-29

申请号：US13949449

申请日：2013-07-24

Applicant: STMicroelectronics International N.V.

Inventor： Nishu Kohli ,  Shishir Kumar

IPC: G11C7/22

CPC classification number: G11C11/419 ,  G11C7/227

Abstract: A write is performed to a first cell of a memory at a first row and column during a first memory access cycle. A memory access operation is made to a second cell at a second row and column during an immediately following second memory access cycle. If the memory access is a read from the second cell and the second row is the same as the first row, or if the memory access is a write to the second cell and the second row is the same as the first row and the second column is different than the first column, then a simultaneous operation is performed during the second memory access cycle. The simultaneous operation is an access of the second cell (for read or write) and a re-write of data from the first memory access cycle write operation back to the first cell.

Abstract translation: 在第一存储器访问周期期间在第一行和列处对存储器的第一单元执行写入。 在紧接着的第二存储器访问周期期间，在第二行和列处对第二单元进行存储器存取操作。 如果存储器访问是从第二单元读取并且第二行与第一行相同，或者如果存储器访问是对第二单元的写入，并且第二行与第一行和第二列相同 与第一列不同，则在第二存储器访问周期期间执行同时操作。 同时操作是第二单元（用于读取或写入）的访问以及从第一存储器访问周期写入操作重新写入数据到第一单元。

公开(公告)号：US20150024683A1

公开(公告)日：2015-01-22

申请号：US14332994

申请日：2014-07-16

Applicant: STMicroelectronics International N.V.

Inventor： Jafer Hussain

IPC: G06K7/10 ,  H04W76/02 ,  H04W28/04 ,  H04B5/00

CPC classification number: G06K7/10039 ,  G06K7/10128 ,  G06K7/10138 ,  G06K7/10237 ,  G06K7/10297 ,  H04B5/0031 ,  H04B5/0062 ,  H04W74/085 ,  H04W76/14

Abstract: A NFC reader is connected for communication to NFC devices such as an NFC-A device and an RF barcode device. The reader detects and logs the active and sleep intervals of the RF barcode device in response to receipt of periodically received UID communications. The transmission and reception of data to and from each NFC-A device is then synchronized to occurs only when the RF barcode device is in a sleep interval between UID communications.

Abstract translation: 连接NFC读取器用于与诸如NFC-A设备和RF条形码设备的NFC设备通信。 响应于接收到周期性接收的UID通信，读取器检测并记录RF条形码设备的活动和睡眠间隔。 然后，每个NFC-A设备的数据的发送和接收被同步，仅当RF条形码设备处于UID通信之间的睡眠间隔时才发生。

公开(公告)号：US08938577B2

公开(公告)日：2015-01-20

申请号：US14288153

申请日：2014-05-27

Applicant: STMicroelectronics International N.V.

Inventor： Sandeep Rohilla

IPC: G06F12/00 ,  G06F13/28

CPC classification number: G06F13/287 ,  G11C7/10 ,  G11C7/103 ,  G11C7/1036 ,  G11C7/1087

Abstract: In managing incoming bus traffic storage for store cell memory (SCM) in a sequential-write, random-read system, a priority encoder system can be used to find a next empty cell in the sequential-write step. Each cell in the SCM has a bit that indicates whether the cell is full or empty. The priority encoder encodes the next empty cell using these bits and the current write pointer. The priority encoder can also find next group of empty cells by being coupled to AND operators that are coupled to each group of cells. Further, a cell locator selector selects a next empty cell location among priority encoders for cell groups of various sizes according to an opcode by appending ‘0’s to cell locations outputs from priority encoders that are smaller than the size of the SCM.

Abstract translation: 在顺序写入随机读取系统中管理存储单元存储器（SCM）的输入总线流量存储器时，优先级编码器系统可用于在顺序写入步骤中找到下一个空单元。 SCM中的每个单元格都有一个位，表示单元格是满还是空。 优先编码器使用这些位和当前写指针对下一个空单元进行编码。 优先编码器还可以通过耦合到耦合到每组单元的AND运算符来找到下一组空单元。 此外，单元定位器选择器根据操作码，通过将小于等于小于SCM大小的优先编码器的单元位置输出相加0来选择各种尺寸的单元组的优先编码器中的下一个空单元位置。

公开(公告)号：US20140375358A1

公开(公告)日：2014-12-25

申请号：US13922483

申请日：2013-06-20

Applicant: STMicroelectronics International N.V.

Inventor： Surendra Kumar

IPC: H03K19/0175

CPC classification number: H03K19/017509 ,  H03K19/00315 ,  H03K19/018521

Abstract: A circuit includes a first input transistor and a first voltage divider coupled to a source of the first input transistor and a second input transistor and a second voltage divider coupled to a source of the second input transistor. A first set of series connected transistors include a first transistor with a gate coupled to the first input transistor source and a second transistor with a gate coupled to a tap of the first voltage divider. A second set of series connected transistors include a third transistor with a gate coupled to the second input transistor source and a fourth transistor with a gate coupled to a tap of the second voltage divider. An output is coupled to the sources of the first and second input transistors. The first and second sets are coupled to one of the first input transistor drain or second input transistor drain.

Abstract translation: 电路包括耦合到第一输入晶体管的源极的第一输入晶体管和第一分压器以及耦合到第二输入晶体管的源极的第二输入晶体管和第二分压器。 第一组串联晶体管包括具有耦合到第一输入晶体管源的栅极的第一晶体管和耦合到第一分压器的抽头的栅极的第二晶体管。 第二组串联连接的晶体管包括具有耦合到第二输入晶体管源的栅极的第三晶体管和具有耦合到第二分压器的抽头的栅极的第四晶体管。 输出耦合到第一和第二输入晶体管的源极。 第一和第二组耦合到第一输入晶体管漏极或第二输入晶体管漏极之一。

公开(公告)号：US08918689B2

公开(公告)日：2014-12-23

申请号：US12871045

申请日：2010-08-30

Applicant: Anirudha Kulkarni ,  Jasvir Singh

Inventor： Anirudha Kulkarni ,  Jasvir Singh

IPC: G06F3/00 ,  G01R31/3185 ,  G01R31/3187 ,  G01R31/319 ,  G11C29/12 ,  G11C29/32

CPC classification number: G01R31/318563 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318538 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318594 ,  G01R31/318597 ,  G01R31/3187 ,  G01R31/31922 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/26 ,  G11C29/32 ,  G11C2029/3202

Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.

Abstract translation: 集成电路被配置为接收测试时钟输入，并且包括经配置以从测试时钟输入产生测试时钟的电路以及被配置为在测试模式中使用测试时钟的测试电路。

公开(公告)号：US08829943B2

公开(公告)日：2014-09-09

申请号：US13656079

申请日：2012-10-19

Applicant: STMicroelectronics International N.V.

Inventor： Daljeet Kumar

IPC: H03K5/153

CPC classification number: H03K5/24 ,  H04B3/46

Abstract: An analog disconnection envelope detection circuit having a low power supply detects a high speed, high differential voltage disconnect state on a data line. Level-shifting circuitry shifts the voltage level of two input signals by the value of a detection threshold voltage, generates differential signals used to indicate conditions of the input signals, and mitigates effects of input differential signal common-mode voltage on the detection operation. Circuitry is provided to equalize VDS of detecting tail current sources, thereby eliminating errors resulting from VDS mismatch of tail current sources. Comparator circuitry compares the sets of differential signals and indicates when the absolute difference between the two input signals is greater than a reference voltage. Output circuitry generates a disconnect signal corresponding to the disconnect condition. When compared to conventional disconnect detection circuitry, the disclosed circuit utilizes a relatively low supply voltage to detect high differential voltage disconnect conditions with improved accuracy.

Abstract translation: 具有低电源的模拟断路包络检测电路检测数据线上的高速，高差分电压断开状态。 电平移位电路通过检测阈值电压的值移位两个输入信号的电压电平，产生用于指示输入信号条件的差分信号，并减轻输入差分信号共模电压对检测操作的影响。 提供电路以均衡检测尾电流源的VDS，从而消除由尾电流源的VDS失配引起的误差。 比较器电路比较差分信号的集合，并指示两个输入信号之间的绝对差大于参考电压的时间。 输出电路产生对应于断开条件的断开信号。 当与常规断开检测电路相比时，所公开的电路利用相对较低的电源电压来以更高的精度来检测高差分电压断开条件。