公开(公告)号：US20020027475A1

公开(公告)日：2002-03-07

申请号：US09886852

申请日：2001-06-21

Applicant: STMicroelectronics S.A.

Inventor： Didier Belot

IPC: H03F003/45

CPC classification number: H03F3/191 ,  H03F3/45089 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45316 ,  H03F2203/45386 ,  H03F2203/45554 ,  H03F2203/45704

Abstract: The amplifier includes an input amplifier stage, an output amplifier stage cascode-connected with the input amplifier stage, and a load stage connected to the output stage. The load stage includes a plurality of circuits each including a capacitive component and an inductive component having a Q greater than 10, and having respective different resonant frequencies. All the gain curves respectively associated with all the circuits have, to within a stated tolerance, the same maximum gain value at the resonant frequencies. The gain curves respectively associated with two circuits having respective immediately adjacent resonant frequencies overlap below a threshold 3 dB, to within a stated tolerance, below the maximum gain value.

Abstract translation: 放大器包括输入放大器级，与输入放大级级共源共栅放大器级的输出放大器级和连接到输出级的负载级。 负载级包括多个电路，每个电路包括电容分量和Q大于10的电感分量，并且具有各自不同的谐振频率。 分别与所有电路相关联的所有增益曲线在所述公差内具有在谐振频率下相同的最大增益值。 分别与具有相应的紧邻谐振频率的两个电路相关联的增益曲线重叠在阈值3dB以下，达到所述公差之内，低于最大增益值。

公开(公告)号：US20020017868A1

公开(公告)日：2002-02-14

申请号：US09770760

申请日：2001-01-25

Applicant: STMicroelectronics S.A.

Inventor： Jean-Pierre Blanc

IPC: H01J029/98

CPC classification number: H04N9/68 ,  H04N5/57 ,  H04N5/68 ,  H04N9/73

Abstract: A process for color adjustment of a color monitor including a cathode-ray tube and a brightness adjustment module includes providing a nominal brightness signal downstream of a white level adjustment module for adjusting a white level and upstream of a black level adjustment module for adjusting a black level. The process also includes setting a voltage required to obtain a black color image, setting a voltage required to obtain a white color image, providing the nominal brightness signal upstream of the white level adjustment module, and setting the voltage required to obtain the black color image.

Abstract translation: 包括阴极射线管和亮度调节模块的彩色监视器的颜色调整过程包括在白电平调节模块的下游提供用于调整白电平的标称亮度信号和用于调节黑色的黑电平调节模块的上游 水平。 该过程还包括设置获得黑色图像所需的电压，设置获得白色图像所需的电压，提供白平衡调节模块上游的标称亮度信号，以及设置获得黑色图像所需的电压 。

公开(公告)号：US20020013876A1

公开(公告)日：2002-01-31

申请号：US09859207

申请日：2001-05-16

Applicant: STMicroelectronics S.A.

Inventor： Francesco La Rosa

IPC: G06F012/00 ,  G11C005/00 ,  G11C029/00

CPC classification number: G06F11/1068 ,  G11C16/10

Abstract: An electrically erasable and programmable memory includes a memory array having memory cells connected to word lines and bit lines. The bit lines are arranged in columns. The memory also includes read circuits connected to the bit lines and programming latches connecting the bit lines to a programming line. The memory includes a device to break the conductive paths connecting the memory cells of a column to the read circuits when data has been loaded into the latches of the column, without breaking the conductive paths that connect the latches of the column to the read circuits.

Abstract translation: 电可擦除可编程存储器包括具有连接到字线和位线的存储器单元的存储器阵列。 位线排列成列。 该存储器还包括连接到位线的读取电路和将位线连接到编程线的编程锁存器。 存储器包括当数据已经被加载到列的锁存器中时断开将列的存储单元连接到读取电路的导电路径的装置，而不会破坏将列的锁存器连接到读取电路的导电路径。

公开(公告)号：US20010055220A1

公开(公告)日：2001-12-27

申请号：US09853254

申请日：2001-05-11

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: G11C011/24 ,  H03H011/26

CPC classification number: G11C11/4099 ,  G11C7/14

Abstract: A voltage regulation device is for a reference cell of a dynamic random access memory arranged in lines and columns and including a plurality of memory cells. The device includes at least one capacitor of a predetermined capacitance which can be discharged during memory access.

Abstract translation: 电压调节装置用于布置成行和列并且包括多个存储单元的动态随机存取存储器的参考单元。 该装置包括至少一个预定电容的电容器，其可以在存储器存取期间被放电。

公开(公告)号：US20010021958A1

公开(公告)日：2001-09-13

申请号：US09737170

申请日：2000-12-14

Applicant: STMicroelectronics S.A.

Inventor： Sebastien Zink ,  Bruno Leconte ,  Paola Cavaleri

IPC: G06F013/00 ,  G06F012/00

CPC classification number: G11C16/10 ,  G11C2216/14

Abstract: An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a sufficient capacity to store a plurality of words, the output of which is coupled to the input of the FLASH memory. A circuit is also included for recording into the buffer memory a series of words to be recorded into the FLASH memory and recording into the FLASH memory the words first recorded into the buffer memory.

Abstract translation: 集成电路存储器包括闪存，其包括用于记录在其输入上呈现的字的电路，而不具有并行同时记录多个字的可能性。 集成电路存储器可以包括具有足够的容量来存储多个字的缓冲存储器，其输出耦合到闪速存储器的输入端。 还包括用于将要记录到FLASH存储器中的一系列字记录到缓冲存储器中并且将首先记录到缓冲存储器中的字记录到FLASH存储器中的电路。

公开(公告)号：US20010004550A1

公开(公告)日：2001-06-21

申请号：US09731090

申请日：2000-12-06

Applicant: STMicroelectronics S.A.

Inventor： Gerard Passemard

IPC: H01L021/4763 ,  H01L021/44 ,  H01L021/31 ,  H01L021/469

CPC classification number: H01L21/76832 ,  H01L21/7681 ,  H01L21/76811 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A interconnection structure of the damascene type is produced on a surface of a microelectronic device that includes at least one dielectric material layer for housing at least one interconnection and at least one interface layer on the dielectric material layer. The interface layer may include at least one SiCH layer and at least one SiOCH layer.

Abstract translation: 镶嵌型的互连结构在微电子器件的表面上产生，该微电子器件的表面包括至少一个电介质材料层，用于容纳介电材料层上的至少一个互连和至少一个界面层。 界面层可以包括至少一个SiCH层和至少一个SiOCH层。

公开(公告)号：US6165265A

公开(公告)日：2000-12-26

申请号：US237378

申请日：1999-01-26

Applicant: Yvon Gris ,  Germaine Troillard ,  Jocelyne Mourier

Inventor： Yvon Gris ,  Germaine Troillard ,  Jocelyne Mourier

IPC: H01L29/73 ,  C30B25/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/331 ,  H01L29/732 ,  C30B25/16 ,  C30B29/06

CPC classification number: C30B29/06 ,  C30B25/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/66287 ,  Y10S117/913

Abstract: The present invention relates to a method of deposition of a silicon layer on a single-crystal silicon substrate 11 , so that the silicon layer is a single-crystal layer, but of different orientation than the substrate, including the steps of defining a window 13 on the substrate; creating inside the window interstitial defects 14 with an atomic proportion lower than one for one hundred; and performing a silicon deposition 15 in conditions generally corresponding to those of an epitaxial deposition, but at a temperature lower than 750.degree. C.

Abstract translation: 本发明涉及在单晶硅衬底11上沉积硅层的方法，使得硅层是单晶层，但是具有与衬底不同的取向，包括以下步骤：限定窗口13 在基材上 在窗口内创建间隙缺陷14，原子比例低于一百; 并且在通常对应于外延沉积的条件下，但在低于750℃的温度下进行硅沉积15。

公开(公告)号：US6156609A

公开(公告)日：2000-12-05

申请号：US298233

申请日：1999-04-23

Applicant: Jean-Michel Mirabel

Inventor： Jean-Michel Mirabel

IPC: H01L21/8247 ,  H01L21/336

CPC classification number: H01L27/11526 ,  H01L27/11546

Abstract: The present invention relates to a method of manufacturing, in a P-type substrate including active areas separated by field oxide areas, heavily-doped stop-channel regions under portions of the field insulation areas, more lightly-doped P- and N-type areas meant to form MOS transistor wells, and heavily-doped N-type areas meant to form the first electrode of a capacitor, including the steps of performing a high energy N-type implantation in P-channel MOS transistor areas; performing a high energy P-type implantation in N-channel MOS transistor areas; performing a high energy P-type implantation in stop-channel areas and in capacitor areas; and performing a low energy N-type implantation, masked by the field oxide.

Abstract translation: 本发明涉及在包括由场氧化物区域分离的有源区域的P型衬底中制造在场绝缘区域的部分下的重掺杂的截止沟道区域的方法，更轻掺杂的P型和N型 旨在形成MOS晶体管阱的区域和意图形成电容器的第一电极的重掺杂N型区域，包括以下步骤：在P沟道MOS晶体管区域中执行高能N型注入; 在N沟道MOS晶体管区域进行高能量P型注入; 在停止通道区域和电容器区域中进行高能P型注入; 并执行由场氧化物掩蔽的低能N型注入。

公开(公告)号：US6141254A

公开(公告)日：2000-10-31

申请号：US355064

申请日：1999-11-26

Applicant: Jean Devin ,  Alessandro Brigati ,  Bruno Leconte

Inventor： Jean Devin ,  Alessandro Brigati ,  Bruno Leconte

IPC: G11C16/02 ,  G11C16/10 ,  G11C16/12 ,  G11C16/00

CPC classification number: G11C16/12 ,  G11C16/10

Abstract: This invention relates to a method for programming a Flash-EPROM type memory (1) comprising words of memory cells arranged in rows (23) and columns (31), in which a floating-gate transistor (7) acts as a storage device, the floating-gate transistors of the memory cells (2-9) in the same word (10) have their control gate connected to the same word line connection (30) and their source connected to the same main electrode (29) of a selection transistor (26), the other main electrode (28) of which is connected to a vertical word source connection (25), in which M memory cells (2, 2b) are programmed simultaneously in N different words (10, 200) during a single programming cycle, where M is less than the number P of memory cells in a word, and where M, N and P are integer numbers.

Abstract translation: PCT No.PCT / FR98 / 00111 Sec。 一九九九年十一月二十二日 102（e）日期1999年11月26日PCT提交1998年1月22日PCT公布。 出版物WO98 / 33187 日期：1998年7月30日本发明涉及一种用于编程闪存EPROM型存储器（1）的方法，该存储器包括排列成行（23）和列（31）的存储单元的字，其中浮栅晶体管（7） 作为存储装置，同一字（10）中的存储单元（2-9）的浮栅晶体管的控制栅极连接到相同的字线连接（30），并且其源极连接到相同的主电极 选择晶体管（26）的另一主电极（28）连接到垂直字源连接（25），其中M个存储单元（2,2b）以N个不同字（10 ，200），其中M小于一个字中的存储器单元的数量P，并且其中M，N和P是整数。

公开(公告)号：US6141103A

公开(公告)日：2000-10-31

申请号：US271038

申请日：1999-03-17

Applicant: Jacques Pinaton ,  Olivier Diop ,  Pascal Lambert

Inventor： Jacques Pinaton ,  Olivier Diop ,  Pascal Lambert

IPC: G01B11/06 ,  G01J4/00

CPC classification number: G01B11/0641

Abstract: A method is to characterize a process of ion implantation and includes a step of the measurement, by a spectroscopic ellipsometer, of the ellipsometric parameters (tan.psi., cos.delta.)of a film of organic resin present on the surface of a wafer that has received ion bombardment. The film of resin includes at least one upper layer of carbonized or damaged resin.

Abstract translation: 方法是表征离子注入的过程，并且包括通过分光椭偏仪测量存在于已经接收的晶片表面上的有机树脂膜的椭偏参数（tan psi，cosδ）的步骤 离子轰击。 树脂膜包括至少一层碳化或损坏的树脂上层。