公开(公告)号：US20030181011A1

公开(公告)日：2003-09-25

申请号：US10351281

申请日：2003-01-24

Applicant: STMicroelectronics S.r.I.

Inventor： Giuseppe Curro ,  Barbara Fazio

IPC: H01L021/336

CPC classification number: H01L29/7813 ,  H01L29/4933

Abstract: A process for forming a trench gate power MOS transistor includes forming an epitaxial layer having a first type of conductivity on a semiconductor substrate, and forming a body region having a second type of conductivity on the epitaxial layer. A gate trench is formed in the body region and in the epitaxial layer. The process further includes countersinking upper portions of the gate trench, and forming a gate dielectric layer on surfaces of the gate trench including the upper portions thereof. A gate conducting layer is formed on surfaces of the gate dielectric layer for defining a gate electrode. The gate conducting layer has a thickness that is insufficient for completely filling the gate trench so that a residual cavity remains therein. The residual cavity is filled with a filler layer. The gate conducting layer is removed from an upper surface of the body region while using the filler layer as a self-aligned mask. The edge surfaces of the gate conducting layer are oxidized. Source regions are formed by implanting dopants in the body region while using the oxidized edge surfaces as a self-aligned mask, and the implanted dopants are diffused in the body region.

Abstract translation: 形成沟槽栅极功率MOS晶体管的工艺包括在半导体衬底上形成具有第一导电类型的外延层，并在外延层上形成具有第二导电类型的体区。 在体区域和外延层中形成栅极沟槽。 该工艺还包括锪孔栅极沟槽的上部，以及在包括其上部的栅极沟槽的表面上形成栅极电介质层。 栅极导电层形成在用于限定栅电极的栅极电介质层的表面上。 栅极导电层的厚度不足以完全填充栅极沟槽，从而残留在其中的空腔。 残留的空腔填充有填料层。 在使用填充层作为自对准掩模的同时，从体区的上表面除去栅极导电层。 栅极导电层的边缘表面被氧化。 源区域通过在使用氧化边缘表面作为自对准掩模的同时在体区中注入掺杂剂而形成，并且注入的掺杂剂在体区中扩散。

公开(公告)号：US20030171004A1

公开(公告)日：2003-09-11

申请号：US10379490

申请日：2003-03-04

Applicant: STMicroelectronics S.r.I.

Inventor： Michele Vulpio

IPC: H01L021/31 ,  C23C016/00

CPC classification number: H01L21/02126 ,  C23C16/30 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/3122 ,  Y10T428/31663

Abstract: A method is for low-dielectric-constant film deposition on a surface of a semiconductor substrate. The deposition may be by chemical vapor deposition (CVD) techniques and may include a wide class of precursor monomeric compounds, namely organosilanes.

Abstract translation: 一种用于半导体衬底表面上的低介电常数膜沉积的方法。 沉积可以通过化学气相沉积（CVD）技术，并且可以包括广泛类型的前体单体化合物，即有机硅烷。

公开(公告)号：US20030149831A1

公开(公告)日：2003-08-07

申请号：US10331177

申请日：2002-12-27

Applicant: STMicroelectronics S.r.I.

Inventor： Emanuele Confalonieri ,  Marco Sforzin

IPC: G06F012/00

CPC classification number: G06F11/1072

Abstract: A decoding structure for a memory device with a control code is used in a memory including a matrix of memory cells grouped into pages to each of which a block of control information is associated, and a plurality of reading elements for reading a plurality of pages in parallel. The decoding structure selectively connects each reading element to a plurality of memory cells, and selectively connects each memory cell to a plurality of reading elements.

Abstract translation: 具有控制码的存储器件的解码结构被用于存储器中的存储器，该存储器包括被分组成一页的存储器单元矩阵，每个存储器单元的一个控制信息块相关联，以及多个用于读取多个页面的读取元件 平行。 解码结构将每个读取元件选择性地连接到多个存储单元，并且将每个存储单元选择性地连接到多个读取元件。

公开(公告)号：US20030146460A1

公开(公告)日：2003-08-07

申请号：US10327704

申请日：2002-12-20

Applicant: STMicroelectronics S.r.I

Inventor： Raffaele Zambrano ,  Cesare Artoni

IPC: G11C007/00 ,  G11C029/00 ,  H01L029/76 ,  H01L029/94 ,  H01L027/108

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75 ,  H01L28/91

Abstract: A memory cell of a stacked type is formed by a MOS transistor and a ferroelectric capacitor. The MOS transistor is formed in an active region of a substrate of semiconductor material and comprises a conductive region. The ferroelectric capacitor is formed on top of the active region and comprises a first and a second electrodes separated by a ferroelectric region. A contact region connects the conductive region of the MOS transistor to the first electrode of the ferroelectric capacitor. The ferroelectric capacitor has a non-planar structure, formed by a horizontal portion and two side portions extending transversely to, and in direct electrical contact with, the horizontal portion.

Abstract translation: 堆叠型存储单元由MOS晶体管和铁电电容器形成。 MOS晶体管形成在半导体材料的衬底的有源区中，并且包括导电区域。 铁电电容器形成在有源区的顶部，并且包括由铁电区域分开的第一和第二电极。 接触区域将MOS晶体管的导电区域与铁电体电容器的第一电极连接。 铁电电容器具有非水平部分形成的非平面结构，该水平部分横向于与水平部分直接电接触延伸的两个侧部。

公开(公告)号：US20030109183A1

公开(公告)日：2003-06-12

申请号：US10243972

申请日：2002-09-12

Applicant: STMicroelectronics S.r.I. ,  Hewlett-Packard Company

Inventor： Ubaldo Mastromatteo ,  Mauro Bombonati ,  Daniela Morin ,  Marta Mottura ,  Mauro Marchi

IPC: H01R009/22

CPC classification number: B81C1/00269 ,  H01L21/185 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05181 ,  H01L2224/05624 ,  H01L2224/10126 ,  H01L2224/10135 ,  H01L2224/13021 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13124 ,  H01L2224/13164 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/812 ,  H01L2224/81201 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/013

Abstract: A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate. The bonding regions are preferably formed by a thick layer of a material chosen from among aluminum, copper and nickel, covered by a thin layer of a material chosen from between palladium and platinum. Spacing regions ensure exact spacing between the two wafers.

公开(公告)号：US20030090591A1

公开(公告)日：2003-05-15

申请号：US10243081

申请日：2002-09-12

Applicant: STMicroelectronics S.r.I.

Inventor： Davide Concion ,  Emiliano Piccinelli ,  Danilo Pau

IPC: H04N005/14

CPC classification number: H04N19/40 ,  H04N19/59

Abstract: A process for format conversion of DCT macroblocks in an MPEG video bitstream that are divided into blocks, each of which includes a plurality of microblocks. In each DCT block, the significant frequencies are identified and preserved, isolating a corresponding microblock preferably consisting of the microblock on the top left of each block and setting to zero the coefficients of the remaining microblocks. On the microblock thus isolated there is performed an inverse discrete cosine transform, and the microblock thus obtained is merged with the homologous microblocks obtained from the other blocks comprised in a respective starting macroblock, so as to give rise to a merging block. The merging block thus obtained undergoes a discrete cosine transform so as to obtain a final block, which can be assembled into a macroblock with converted format.

Abstract translation: MPEG视频比特流中的DCT宏块的格式转换处理，被分成块，每个块包括多个微块。 在每个DCT块中，识别和保存有效频率，隔离优选地由每个块的左上角的微块组成的相应微块，并将剩余微块的系数设置为零。 在这样隔离的微块上，执行逆离散余弦变换，并且由此获得的微块与从包含在相应起始宏块中的其他块获得的同源微块合并，以产生合并块。 如此获得的合并块经历离散余弦变换，以获得最终的块，其可以被组合成具有转换格式的宏块。

公开(公告)号：US20030080804A1

公开(公告)日：2003-05-01

申请号：US09998902

申请日：2001-10-31

Applicant: STMicroelectronics S.r.I.

Inventor： Davide Torrisi ,  Ignazio Martines

IPC: G05F001/10

CPC classification number: H02M3/073 ,  H02M2003/071 ,  H02M2003/075

Abstract: A negative charge pump circuit includes a cascade connection of a plurality of charge pump stages, each stage including at least a charge capacitance and a pass transistor driven by a corresponding phase signal. An input stage may be coupled to an input reference potential. An output stage may include an output terminal for generating a first pumped voltage. In addition, the charge pump circuit may further include a second output stage connected downstream to the input stage and including a second output terminal for generating a second pumped potential. The architecture may also be implemented in positive charge pump circuits.

Abstract translation: 负电荷泵电路包括多个电荷泵级的级联，每级包括至少一个充电电容和由相应的相位信号驱动的通过晶体管。 输入级可以耦合到输入参考电位。 输出级可以包括用于产生第一泵送电压的输出端子。 此外，电荷泵电路还可以包括连接到输入级的下游的第二输出级，并且包括用于产生第二泵浦电位的第二输出端。 该结构也可以在正电荷泵电路中实现。

公开(公告)号：US20030071689A1

公开(公告)日：2003-04-17

申请号：US10244113

申请日：2002-09-13

Applicant: STMicroelectronics S.r.I.

Inventor： Antonio Magazzu ,  Benedetto Marco Marletta ,  Giuseppe Gramegna ,  Alessandro D'Aquila

IPC: H03L007/00

CPC classification number: H03K17/162 ,  H03L7/0891 ,  H03L7/183

Abstract: A method and a circuit for minimizing glitches in phase-locked loops is presented. The circuit includes an input terminal connected to an input of a phase detector; a series of a charge pump generator, a filter and a voltage controlled oscillator connected downstream of the phase detector; and a frequency divider feedback connected between an output of the voltage controlled oscillator and a second input of the phase detector. The circuit provides for the inclusion of a compensation circuit connected between the charge pump generator and the filter to absorb an amount of the charge passed therethrough. This compensation circuit includes a storage element connected in series to two switches. The first switch is coupled to and controlled by an output of the charge pump and the second switch is coupled to and controlled by an output of a phase detector.

公开(公告)号：US20030068037A1

公开(公告)日：2003-04-10

申请号：US09974176

申请日：2001-10-10

Applicant: STMicroelectronics S.r.I.

Inventor： Guido Bertoni ,  Luca Breveglieri ,  Pasqualina Fragneto

IPC: H04L009/00

CPC classification number: G06F7/724

Abstract: A circuit for computing the inner of scalar product of two vectors in a finite Galois field defined by a generator polynomial, wherein each vector includes at least two elements belonging to said finite field, comprises one or more look-up tables storing digital words indicative of said possible combinations and said possible reductions. The digital words in question are defined as a function of the second elements of said vectors and the generator polynomial of the field. The input register(s) and the look-up table(s) are configured to co-operate in a plurality of subsequent steps to generate at each step a partial product result identified by at least one of digital word addressed in a corresponding look-up table as a function of the digital signals stored in the input register(s). The circuit also includes an accumulator unit for adding up the partial results generated at each step to give a final product result deriving from accumulation of said partial results.

Abstract translation: 一种用于计算由生成多项式定义的有限伽罗瓦域中的两个向量的标量积的内部的电路，其中每个向量包括属于所述有限域的至少两个元素，包括一个或多个查找表，其存储指示 说可能的组合和所述可能的减少。 所讨论的数字词被定义为所述向量的第二元素和场的生成多项式的函数。 输入寄存器和查找表被配置为在多个后续步骤中协作以在每个步骤处生成由相应查找表中寻址的数字字中的至少一个标识的部分乘积结果， 作为存储在输入寄存器中的数字信号的函数。 该电路还包括用于将在每个步骤产生的部分结果相加以产生从所述部分结果的积累得到的最终产品结果的累加器单元。

公开(公告)号：US20030032244A1

公开(公告)日：2003-02-13

申请号：US10261987

申请日：2002-10-01

Applicant: STMicroelectronics S.r.I.

Inventor： Daniela Peschiaroli ,  Alfonso Maurelli ,  Elisabetta Palumbo ,  Fausto Piazza

IPC: H01L021/336

CPC classification number: H01L27/11526 ,  H01L27/1052 ,  H01L27/11541

Abstract: A method for manufacturing an integrated circuit having a memory device and a logic circuit includes forming a plurality of first transistors in a first portion of a semiconductor substrate, a plurality of second transistors in a second portion of the semiconductor substrate, and a plurality of memory cells in a third portion of the semiconductor substrate. A matrix mask used for selectively removing a dielectric layer from the first and third portions of the semiconductor substrate allows dielectric to remain on a floating gate of the plurality of memory cells and on the gate electrodes of the plurality of first transistors. A control gate is then formed on the floating gate, which is separated by the dielectric. Portions of the gate electrodes for the plurality of first transistors are left free so that contact is made with the transistors.