公开(公告)号：US09706147B2

公开(公告)日：2017-07-11

申请号：US14600887

申请日：2015-01-20

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Cedric Tubert

IPC: H04N1/03 ,  H04N5/374 ,  H01L27/146 ,  H04N5/378

CPC classification number: H04N5/3741 ,  H01L27/14612 ,  H01L27/14636 ,  H01L27/14641 ,  H01L27/14643 ,  H04N5/378

Abstract: An image sensor includes a first photodiode with associated first sense node and a second photodiode with associated second sense node. A first transistor has its control node coupled to the first sense node and a second transistor has its control node coupled to the second sense node. The conduction paths (for example, source-drain paths) of the first and second transistors are coupled in series between first and second column lines associated with a column of the image sensor array. Switches control connection of the first and second column lines in two modes: one mode where a voltage is applied to the first column line and data from one of the photodiodes is read out by the second column line; and another mode where a voltage is applied to the second column line and data from the other of the photodiodes is read out by the first column line.

公开(公告)号：US20170176578A1

公开(公告)日：2017-06-22

申请号：US15168535

申请日：2016-05-31

Applicant: STMicroelectronics (Research & Development) Limited ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Bruce Rae ,  Pascal Mellot ,  John Kevin Moore ,  Graeme Storm

IPC: G01S7/486 ,  H01L31/16 ,  H01L31/107 ,  H01L27/144 ,  G01S17/10 ,  G01S17/88

CPC classification number: G01S7/4863 ,  G01S7/4865 ,  G01S7/487 ,  G01S7/497 ,  G01S17/003 ,  G01S17/10 ,  G01S17/102 ,  G01S17/58 ,  G01S17/87 ,  G01S17/88 ,  G01S17/89 ,  H01L27/1443 ,  H01L27/1446 ,  H01L31/107 ,  H01L31/165

Abstract: A ranging apparatus includes an array of light sensitive detectors configured to receive light from a light source which has been reflected by an object. The array includes a number of different zones. Readout circuitry including at least one read out channel is configured to read data output from each of the zones. A processor operates to process the data output to determine position information associated with the object.

公开(公告)号：US20170133520A1

公开(公告)日：2017-05-11

申请号：US15410230

申请日：2017-01-19

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Karine Saxod ,  Marika Sorrieul

IPC: H01L31/0203 ,  H01L31/18 ,  H01L31/02

CPC classification number: H01L23/562 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/315 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/13 ,  H01L24/17 ,  H01L24/29 ,  H01L24/30 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/94 ,  H01L25/0657 ,  H01L27/14618 ,  H01L27/14683 ,  H01L31/02005 ,  H01L31/0203 ,  H01L31/1876 ,  H01L2224/1329 ,  H01L2224/13291 ,  H01L2224/14179 ,  H01L2224/2929 ,  H01L2224/29291 ,  H01L2224/30135 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73257 ,  H01L2224/81862 ,  H01L2224/81874 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/16315 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/13099

Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.

公开(公告)号：US09647826B2

公开(公告)日：2017-05-09

申请号：US14689107

申请日：2015-04-17

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Abdelaziz Goulahsen ,  Gilles Ries

IPC: H03M13/00 ,  H04L7/00 ,  G09G5/00 ,  G06F13/42 ,  H04L1/16

CPC classification number: H04L7/0054 ,  G06F13/4265 ,  G06F13/4295 ,  G09G5/006 ,  G09G5/12 ,  G09G2370/10 ,  H04L1/1607

Abstract: A system may include a first device, a second device, a third device, and a serial link between the second device and the third device. The first device may be configured to deliver to the second device an information stream having a transmission fault tolerance associated with a transmission by the second device to the third device over the serial link. A related method may include, during the transmission over the serial link, phases for synchronization between the second and third devices, and during each synchronization phase, the first device may continue to deliver the information stream to the second device.

公开(公告)号：US09600397B2

公开(公告)日：2017-03-21

申请号：US14467270

申请日：2014-08-25

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Nicolas Sauzede ,  Alexandre Nabais ,  Florian Guillochon

IPC: G06F9/44 ,  G06F11/36 ,  G06F9/445

CPC classification number: G06F11/362 ,  G06F9/44521

Abstract: When a module is loaded by the operating system kernel, dynamic information of the module, such as the memory addresses of the different sections of the module allocated by the operating system, is stored in a known variable, which is subsequently accessible by the debugging tool. Furthermore, an interrupt instruction that will allow the debugger to interrupt the running of the operating system following the complete loading of the module is inserted into the debugging tool in such a way as to retrieve the dynamic information necessary for the debugging of the module.

公开(公告)号：US09595552B2

公开(公告)日：2017-03-14

申请号：US14642100

申请日：2015-03-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Flavien Hirigoyen ,  Emilie Huss

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14603 ,  H01L27/1463 ,  H01L27/14683 ,  H01L27/14685

Abstract: A method of simultaneously manufacturing First and second pixels respectively shielded on a first and on a second side are simultaneously manufactured using a process wherein a first insulator is deposited on an active area. A first metal level is deposited and defined, with a first mask, to form a shield on the first side of the first pixel and on the second side of the second pixel, and a line opposite to the shield. A second insulator is deposited, and via openings therein are defined, with a second mask. An overlying second metal level is deposited and defined, with a third mask, to form two connection areas covering the via openings on each side of the first and second pixels. The second and third masks are identical for the first and second pixels.

Abstract translation: 使用其中第一绝缘体沉积在有源区上的方法同时制造同时制造分别屏蔽在第一和第二侧上的第一和第二像素的方法。 用第一掩模沉积和限定第一金属层，以在第一像素的第一侧和第二像素的第二侧上形成屏蔽，并且与屏蔽件相对的线。 沉积第二绝缘体，并且通过第二掩模限定其中的通孔开口。 用第三掩模沉积和限定覆盖的第二金属层，以形成覆盖第一和第二像素的每一侧上的通孔开口的两个连接区域。 第二和第三掩模对于第一和第二像素是相同的。

公开(公告)号：US20170070029A1

公开(公告)日：2017-03-09

申请号：US15052458

申请日：2016-02-24

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Research & Development) Limited

Inventor： Nicolas Moeneclaey ,  Shatabda Saha

IPC: H01S5/042 ,  G01S17/08 ,  G01S7/484 ,  H01S5/183

CPC classification number: H01S5/0428 ,  G01S7/484 ,  G01S7/4863 ,  G01S7/4865 ,  G01S17/10 ,  G01S17/89 ,  H01S5/183 ,  H05B33/0803 ,  H05B33/0806 ,  H05B33/0842 ,  H05B33/0845

Abstract: An optical pulse emitter includes a light emitting device having a first node coupled to an intermediate node via a first switch. The intermediate node is coupled to a supply voltage node via a second switch. A capacitor is coupled to the intermediate node. The first, second and third switches are controlled by a control circuit. During a first phase, the second switch is actuated to couple the capacitor to the supply voltage node. During a second phase, the second switch is deactuated and the first switch is actuated to at least partially discharge the capacitor through the light emitting device. During a third phase, discharge current from the capacitor bypasses around the light emitting device.

Abstract translation: 光脉冲发射器包括具有经由第一开关耦合到中间节点的第一节点的发光器件。 中间节点经由第二开关耦合到电源电压节点。 电容器耦合到中间节点。 第一，第二和第三开关由控制电路控制。 在第一阶段期间，第二开关被致动以将电容器耦合到电源电压节点。 在第二阶段期间，第二开关被去激活，并且第一开关被致动以使电容器至少部分地通过发光器件放电。 在第三阶段期间，来自电容器的放电电流绕过发光器件。

公开(公告)号：US20170062298A1

公开(公告)日：2017-03-02

申请号：US15050216

申请日：2016-02-22

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： David Auchere ,  Laurent Marechal ,  Laurent Schwarz ,  Yvon Imbs

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L21/52 ,  H01L23/13 ,  H01L23/498

CPC classification number: H01Q1/38 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/4889 ,  H01L21/52 ,  H01L21/56 ,  H01L23/13 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/315 ,  H01L23/481 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/645 ,  H01L23/66 ,  H01L24/81 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01Q1/2283

Abstract: An electronic device includes a support board having a mounting face and an integrated circuit chip mounted on the mounting face. An encapsulation block embeds the integrated circuit chip, the encapsulation block extending above the integrated circuit chip and around the integrated circuit chip on the mounting face of the support board. The encapsulation block includes a front face with a hole passing through the encapsulation block to uncovering at least part of an electrical contact. A layer made of an electrically conducting material fills the hole to make electrical connection to the electrical contact and further extends over the front face of the encapsulation block.

Abstract translation: 电子设备包括具有安装面的支撑板和安装在安装面上的集成电路芯片。 封装块嵌入集成电路芯片，封装块在集成电路芯片上方延伸，并围绕集成电路芯片在支撑板的安装面上。 封装块包括具有穿过封装块的孔的前表面以露出至少一部分电触点。 由导电材料制成的层填充孔以与电接触电连接并且进一步在封装块的前表面上延伸。

公开(公告)号：US09565375B1

公开(公告)日：2017-02-07

申请号：US14930834

申请日：2015-11-03

Applicant: STMICROELECTRONICS (RESEARCH & DEVELOPMENT) LIMITED ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Jeffrey M. Raynor ,  Alexandre Balmefrezol ,  Laurence Stark

IPC: H01L27/148 ,  H04N5/353 ,  H04N5/378 ,  H01L27/146

CPC classification number: H01L27/14643 ,  H01L27/14603 ,  H01L27/1464 ,  H04N5/3745 ,  H04N5/37452

Abstract: A pixel has a photodiode configured to be sensitive to light. The pixel is arranged to use back side illumination. The pixel has at least one sample and hold capacitor which is arranged on the side of the photodiode remote from a side on which light impinges. The capacitor overlies at least part of the photodiode.

Abstract translation: 像素具有被配置为对光敏感的光电二极管。 像素布置成使用背面照明。 该像素具有至少一个采样和保持电容器，其布置在光电二极管的远离光入射侧的一侧。 电容器覆盖光电二极管的至少一部分。

公开(公告)号：US20170033151A1

公开(公告)日：2017-02-02

申请号：US15290137

申请日：2016-10-11

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Flavien Hirigoyen ,  Emilie Huss

IPC: H01L27/146

CPC classification number: H01L27/14623 ,  H01L27/14603 ,  H01L27/1463 ,  H01L27/14683 ,  H01L27/14685

Abstract: A method of simultaneously manufacturing First and second pixels respectively shielded on a first and on a second side are simultaneously manufactured using a process wherein a first insulator is deposited on an active area. A first metal level is deposited and defined, with a first mask, to form a shield on the first side of the first pixel and on the second side of the second pixel, and a line opposite to the shield. A second insulator is deposited, and via openings therein are defined, with a second mask. An overlying second metal level is deposited and defined, with a third mask, to form two connection areas covering the via openings on each side of the first and second pixels. The second and third masks are identical for the first and second pixels.

Abstract translation: 使用其中第一绝缘体沉积在有源区上的方法同时制造同时制造分别屏蔽在第一和第二侧上的第一和第二像素的方法。 用第一掩模沉积和限定第一金属层，以在第一像素的第一侧和第二像素的第二侧上形成屏蔽，并且与屏蔽件相对的线。 沉积第二绝缘体，并且通过第二掩模限定其中的通孔开口。 用第三掩模沉积和限定覆盖的第二金属层，以形成覆盖第一和第二像素的每一侧上的通孔开口的两个连接区域。 第二和第三掩模对于第一和第二像素是相同的。