公开(公告)号：US20150317225A1

公开(公告)日：2015-11-05

申请号：US14266067

申请日：2014-04-30

Applicant: STMicroelectronics International N.V.

Inventor： Harsh Rawat ,  Kedar Janardan Dhori ,  Vinay Kumar ,  PraveenKumar Verma

IPC: G06F11/20

CPC classification number: G11C29/702 ,  G06F11/2094 ,  G06F2201/85

Abstract: Repair control logic for a safe memory having redundant elements is provided. The repair control logic includes comparison logic including, for each bit slice of a memory array, a comparator circuit configured to determine whether a location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of the memory array, and data switching logic including, for each bit slice of the memory array, a switching circuit, responsive to a determination that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch data from the associated bit slice to an adjacent bit slice of the memory array.

Abstract translation: 提供了具有冗余元件的安全存储器的修复控制逻辑。 修复控制逻辑包括比较逻辑，包括对于存储器阵列的每个位片，比较器电路被配置为确定存储器阵列的关联位片的位置值是否大于存储器阵列的有缺陷位片的位置值 存储器阵列和数据切换逻辑，包括对于存储器阵列的每个位片，响应于相关联的位片的位置值大于缺陷比特片的位置值的确定来切换数据，切换电路 从相关联的位片到存储器阵列的相邻位片。

公开(公告)号：US09177637B1

公开(公告)日：2015-11-03

申请号：US14472166

申请日：2014-08-28

Applicant: STMicroelectronics International N.V.

Inventor： Anuj Grover ,  Gangaikondan Subramani Visweswaran

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/06

CPC classification number: G11C11/419 ,  G11C7/06 ,  G11C7/065 ,  G11C7/1048 ,  G11C2207/002

Abstract: A dual rail SRAM array includes a plurality of columns of memory cells each coupled between two bit lines. A sense amplifier is coupled between each pair of bit lines. Capacitors are positioned between the sense amplifier outputs and the bit lines, thereby separating the sense amplifier from the bit lines. The memory cells are powered with an array supply voltage. The sense amplifier is powered with a peripheral supply voltage. During a read operation of the memory array, the bit lines are precharged to the array supply voltage. The sense amplifier is precharged to the peripheral supply voltage or to an intermediate voltage.

Abstract translation: 双轨SRAM阵列包括多个存储单元列，每个存储单元分别耦合在两个位线之间。 读出放大器耦合在每对位线之间。 电容器位于感测放大器输出和位线之间，从而将读出放大器与位线分离。 存储单元由阵列电源电压供电。 读出放大器由周边电源供电。 在存储器阵列的读取操作期间，位线被预充电到阵列电源电压。 读出放大器被预充电到外围电源电压或中间电压。

公开(公告)号：USRE45769E1

公开(公告)日：2015-10-20

申请号：US14222900

申请日：2014-03-24

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Francesco Varone ,  Amedeo Veneroso

IPC: H04M1/00 ,  G06Q20/34 ,  G06F9/445

CPC classification number: G06Q20/341 ,  G06F9/445

Abstract: An IC Card comprises a first device, including a first processor and a first memory unit, to communicate with a handset, and a second device. The second device includes a second processor and a second memory unit, to communicate via a wireless communication with an electronic apparatus external to the handset, the second device providing predetermined services. Each predetermined service is programmed to receive a wireless message from a respective electronic apparatus, to execute a predetermined elaboration operation, and to return a result to the respective electronic apparatus. The second memory unit stores a plurality of additional programs for executing additional elaborations operations, each program being associated to one of the predetermined services. The second device has a run-time environment for executing the additional programs when the corresponding predetermined services receives the wireless message.

Abstract translation: IC卡包括第一设备，包括第一处理器和第一存储器单元，以与手机通信，以及第二设备。 第二设备包括第二处理器和第二存储器单元，用于经由与手机外部的电子设备的无线通信进行通信，第二设备提供预定的服务。 每个预定服务被编程为从相应的电子设备接收无线消息，执行预定的详细操作，并将结果返回到各个电子设备。 第二存储器单元存储用于执行附加精细化操作的多个附加程序，每个程序与预定服务之一相关联。 当相应的预定服务接收到无线消息时，第二设备具有用于执行附加程序的运行时环境。

公开(公告)号：US09167023B2

公开(公告)日：2015-10-20

申请号：US14078118

申请日：2013-11-12

Applicant: STMicroelectronics International N.V.

Inventor： Surinder Pal Singh ,  Kaushik Saha

IPC: G01R19/18 ,  H04L29/08 ,  G01R21/133 ,  G01R19/22 ,  H04L12/24

CPC classification number: H04L67/025 ,  G01R19/22 ,  G01R21/133 ,  H04L41/32

Abstract: A system for power measurement in an electronic device includes a sensing unit, an analog-to-digital converter (ADC) and a controller. The sensing unit senses voltage across a power source and modulates a carrier signal based on the sensed voltage. The ADC converts a combination of the modulated carrier signal and audio signals received by the electronic device to generate a digitized combined signal and provides the digitized combined signal to the controller. The controller separates digitized modulated carrier signal and digitized audio signals. The digitized modulated carrier signal is demodulated to generate an output signal that provides a measure of the power consumed by the electronic device.

Abstract translation: 电子设备中的功率测量系统包括感测单元，模数转换器（ADC）和控制器。 感测单元感测电源两端的电压，并根据检测到的电压调制载波信号。 ADC转换由电子设备接收的调制载波信号和音频信号的组合，以产生数字化的组合信号，并将数字化的组合信号提供给控制器。 控制器分离数字化调制载波信号和数字化音频信号。 数字化调制载波信号被解调以产生提供电子设备消耗的功率的量度的输出信号。

公开(公告)号：US20150270776A1

公开(公告)日：2015-09-24

申请号：US14222430

申请日：2014-03-21

Applicant: STMicroelectronics International N.V.

Inventor： Ranajay Mallik ,  Jitendra Jain

IPC: H02M3/156

CPC classification number: H02M3/156 ,  H02M2001/0025 ,  Y10T307/406

Abstract: One embodiment of a power management system includes a reservoir configured to collect energy. The system also includes a voltage regulator coupled to the reservoir via an input terminal and configured to convert the energy to an output voltage via an output terminal when enabled. A threshold detector is coupled to the reservoir and is configured to sense the energy and enable the voltage regulator when the energy exceeds a threshold. The system further includes a feedback circuit coupled between the output terminal and the threshold detector, and configured to feedback the output voltage to the threshold detector to compensate for a voltage drop across the threshold detector due to an output current drawn by the load.

Abstract translation: 电力管理系统的一个实施例包括构造成收集能量的储存器。 该系统还包括经由输入端子耦合到储存器的电压调节器，并经配置以在使能时经由输出端子将能量转换成输出电压。 阈值检测器耦合到储存器并且被配置为当能量超过阈值时感测能量并启用电压调节器。 该系统还包括耦合在输出端和阈值检测器之间的反馈电路，并被配置为将输出电压反馈到阈值检测器，以补偿由负载引起的输出电流引起的阈值检测器两端的电压降。

公开(公告)号：US20150268133A1

公开(公告)日：2015-09-24

申请号：US14218482

申请日：2014-03-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V.

Inventor： Om Ranjan ,  Giampiero Borgonovo ,  Deepak Baranwal

IPC: G01M99/00

CPC classification number: G06F11/0736 ,  G05B19/0428 ,  G05B23/0254 ,  G05B2219/2637 ,  G06F11/2205 ,  G06F11/3013

Abstract: A safety system monitors faults in an embedded control system. The embedded control system is modeled to produce one or more model check values by calculating how many clock cycles will pass between an initialization time point and at least one event time point for a specific event. The initialization time point is a certain point in an initialization function of a scheduler in the embedded control system. The at least one event time point is an expected number of clock cycles to pass before a specific event occurs. In operation, the embedded control system is initialized, a current clock cycle counter value is retrieved at a certain point in the initialization, and either an occurrence or an absence of an occurrence of a scheduled event is recognized. A current clock cycle value is recorded upon the recognition, and a mathematic check value is produced from the clock cycle value stored at the certain point in the initialization and the clock cycle value recorded upon the recognition. Subsequently, the model check value is compared to the mathematic check value, and action is taken based on the comparison.

Abstract translation: 安全系统监控嵌入式控制系统中的故障。 嵌入式控制系统被建模为通过计算在特定事件的初始化时间点和至少一个事件时间点之间经过多少个时钟周期来产生一个或多个模型检查值。 初始化时间点是嵌入式控制系统中的调度器的初始化功能中的某一点。 至少一个事件时间点是在特定事件发生之前要通过的期望数量的时钟周期。 在操作中，初始化嵌入式控制系统，在初始化中的某一点检索当前的时钟周期计数器值，并且识别调度事件的发生或不存在。 在识别时记录当前时钟周期值，并且从存储在初始化中的某一点的时钟周期值和在识别时记录的时钟周期值产生数学校验值。 随后，将模型检查值与数学检查值进行比较，并根据比较进行动作。

公开(公告)号：US20150263707A1

公开(公告)日：2015-09-17

申请号：US14216719

申请日：2014-03-17

Applicant: STMicroelectronics International N.V.

Inventor： Ravinder KUMAR

IPC: H03K3/3565

CPC classification number: H03K3/3565

Abstract: A Schmitt Trigger is implemented in FDSOI technology. The Schmitt Trigger includes a first inverting stage having an NMOS and PMOS transistor having their drains tied together. The NMOS and PMOS transistor each have a first gate coupled to the input voltage and a back gate coupled to the output of the Schmitt Trigger.

Abstract translation: 施密特触发器采用FDSOI技术实现。 施密特触发器包括具有连接在一起的NMOS和PMOS晶体管的第一反相级。 NMOS和PMOS晶体管各自具有耦合到输入电压的第一栅极和耦合到施密特触发器的输出的后栅极。

公开(公告)号：US20150179282A1

公开(公告)日：2015-06-25

申请号：US14640601

申请日：2015-03-06

Applicant: STMicroelectronics International N.V.

Inventor： Nishu Kohli

IPC: G11C29/10

CPC classification number: G11C29/10 ,  G01R31/318307 ,  G01R31/318342 ,  G01R31/318371 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/34 ,  G11C11/4063 ,  G11C29/00 ,  G11C29/14 ,  G11C29/24 ,  G11C29/50 ,  G11C29/52 ,  G11C29/54 ,  G11C29/56004 ,  G11C29/56008

Abstract: An embodiment of a method for automated test pattern generation (ATPG), a system for ATPG, and a memory configured for ATPG. For example, an embodiment of a memory includes a first test memory cell, a data-storage memory cell, and a test circuit configured to enable the test cell and to disable the data-storage cell during a test mode.

Abstract translation: 用于自动测试模式生成（ATPG）的方法，用于ATPG的系统和为ATPG配置的存储器的实施例。 例如，存储器的实施例包括第一测试存储器单元，数据存储存储器单元和被配置为使能测试单元并且在测试模式期间禁用数据存储单元的测试电路。

公开(公告)号：US09054637B1

公开(公告)日：2015-06-09

申请号：US14152523

申请日：2014-01-10

Applicant: STMicroelectronics International N.V.

Inventor： Gauri Mittal ,  Kallol Chatterjee

IPC: H03B5/36 ,  H03B5/04 ,  H03B5/06

CPC classification number: H03B5/364 ,  H03B5/04 ,  H03B5/06 ,  H03B2200/0012 ,  H03B2200/0038 ,  H03B2200/0066 ,  H03B2200/0094

Abstract: An amplitude limiting circuit for a crystal oscillator circuit includes a current source configured to supply drive current to the crystal oscillator circuit and a current sensing circuit configured to sense operating current in an inverting transistor of the crystal oscillator circuit. The current comparison circuit functions to compare the sensed operating current to at least a reference current and generate an output signal. A current control circuit generates a control signal for controlling operation of the current source in response to the output signal.

Abstract translation: 晶体振荡器电路的振幅限制电路包括被配置为向晶体振荡器电路提供驱动电流的电流源和被配置为感测晶体振荡器电路的反相晶体管中的工作电流的电流感测电路。 当前比较电路用于将感测的工作电流与至少参考电流进行比较，并产生输出信号。 电流控制电路响应于输出信号产生用于控制电流源的操作的控制信号。

公开(公告)号：US20150145608A1

公开(公告)日：2015-05-28

申请号：US14090759

申请日：2013-11-26

Applicant: STMicroelectronics International N.V.

Inventor： Amit Katyal

IPC: H03K3/03

CPC classification number: H03K3/0315 ,  G05F3/262 ,  H03L7/0995

Abstract: A phase locked loop includes a voltage-controlled oscillator and a current mirror circuit that supplies a drive current to the voltage-controlled oscillator. The current mirror circuit includes a filter between a bias current generator and current mirror transistor. The filter includes a first and a second switch driven in unison with a small duty cycle.

Abstract translation: 锁相环包括压控振荡器和向压控振荡器提供驱动电流的电流镜电路。 电流镜电路包括偏置电流发生器和电流镜晶体管之间的滤波器。 该滤波器包括以小占空比同时驱动的第一和第二开关。