公开(公告)号：US08907284B2

公开(公告)日：2014-12-09

申请号：US13692691

申请日：2012-12-03

Applicant: STMicroelectronics S.A.

Inventor： Hani Sherry ,  Andreia Cathelin ,  Ullrich Pfeiffer ,  Janusz Grzyb ,  Richard Al Hadi

IPC: G01J5/00 ,  G01J5/02 ,  G01J5/34 ,  H03K3/03 ,  G05F3/26

CPC classification number: G01J5/34 ,  G05F3/26 ,  H01Q1/2283 ,  H01Q7/00 ,  H03K3/0315

Abstract: A pixel circuit may include a detection circuit having first and second transistors coupled in series between differential output nodes of an antenna. The antenna may be configured to be sensitive to terahertz radiation. The pixel circuit may also include a capacitor coupled to an intermediate node between the first and second transistors, and control circuitry coupled to control nodes of the first and second transistors. The control circuitry may be configured for selectively applying to the control nodes a gate biasing voltage for biasing the control nodes of the first and second transistors during a detection phase of the pixel circuit, and/or a reset voltage for resetting a voltage stored by the capacitor.

Abstract translation: 像素电路可以包括具有串联耦合在天线的差分输出节点之间的第一和第二晶体管的检测电路。 天线可以被配置为对太赫兹辐射敏感。 像素电路还可以包括耦合到第一和第二晶体管之间的中间节点的电容器，以及耦合到第一和第二晶体管的控制节点的控制电路。 控制电路可以被配置为在像素电路的检测阶段期间选​​择性地向控制节点施加用于偏置第一和第二晶体管的控制节点的栅极偏置电压，和/或用于复位由像素电路存储的电压的复位电压 电容器。

公开(公告)号：US08822332B2

公开(公告)日：2014-09-02

申请号：US13871884

申请日：2013-04-26

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Heimanu Niebojewski ,  Yves Morand ,  Cyrille Le Royer ,  Fabrice Nemouchi

IPC: H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/66477 ,  H01L21/28247 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823475 ,  H01L21/84 ,  H01L29/66545 ,  H01L29/66606

Abstract: A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.

Abstract translation: 一种用于在MOS晶体管上形成栅极，源极和漏极接触的方法，其具有包括被金属栅极硅化物覆盖的多晶硅的绝缘栅极，该栅极由至少一个由第一绝缘材料制成的隔离物包围，该方法包括以下步骤： a）用第二绝缘材料覆盖结构并使第二绝缘材料平整以到达栅极硅化物; b）氧化栅极，使得栅极硅化物掩埋并覆盖氧化硅; c）选择性地去除所述第二绝缘材料; 以及d）用第一导电材料覆盖所述结构，并且将所述第一导电材料一直调整到所述隔离物顶部的较低水平。

公开(公告)号：US20140235186A1

公开(公告)日：2014-08-21

申请号：US14177358

申请日：2014-02-11

Applicant: Institut Polytechnique de Bordeaux ,  STMicroelectronics S.A.

Inventor： Didier Belot ,  Yann Deval ,  Francois Rivet

IPC: H04B1/00

CPC classification number: H04B1/0021 ,  H04B1/0014 ,  H04B1/406 ,  H04B2001/0491 ,  H04L27/2639 ,  H04L27/2642

Abstract: A method for generating a radio frequency signal, wherein a signal to be transmitted is decomposed into a weighted sum of periodic basic signals of different frequencies.

Abstract translation: 一种用于产生射频信号的方法，其中待传输的信号被分解成不同频率的周期性基本信号的加权和。

公开(公告)号：US08799623B2

公开(公告)日：2014-08-05

申请号：US12086971

申请日：2006-12-22

Applicant: Joël Cambonie

Inventor： Joël Cambonie

IPC: G06F15/80 ,  G06F15/78 ,  G06F15/173 ,  G06F9/38 ,  G06F13/368

CPC classification number: G06F15/7867 ,  G06F9/3885 ,  G06F13/368 ,  G06F15/173 ,  G06F15/17381 ,  G06F15/803

Abstract: A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.

Abstract translation: 一种具有N个级别的可重构分层计算机架构，其中N是大于1的整数值，其中所述N个级别包括第一级，包括第一计算块，所述第一级包括第一数据输入，第一数据输出和多个计算节点， 第一连接机构，每个计算节点包括输入端口，功能单元和输出端口，所述第一连接机构能够将每个输出端口连接到彼此的计算节点的输入端口; 以及第二级，包括第二计算块，包括第二数据输入，第二数据输出和通过第二连接装置互连的多个第一计算块，用于选择性地连接每个第一计算块和第二计算块的第一数据输出 数据输入到每个第一数据输入端，并且用于选择性地将每个第一数据输出连接到第二数据输出。

公开(公告)号：US20140167116A1

公开(公告)日：2014-06-19

申请号：US14104993

申请日：2013-12-12

Applicant: STMicroelectronics S.A.

Inventor： Pascal Chevalier ,  Didier Celi ,  Jean-Pierre Blanc ,  Alain Chantre

IPC: H01L29/66 ,  H01L29/737

CPC classification number: H01L29/66242 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/66325 ,  H01L29/737 ,  H01L29/7378

Abstract: The present disclosure is directed to a method that includes exposing a surface of a silicon substrate in a first region between first and second isolation trenches, etching the silicon substrate in the first region to form a recess between the first and second isolation trenches,=; and forming a base of a heterojunction bipolar transistor by selective epitaxial growth of a film comprising SiGe in the recess.

Abstract translation: 本公开涉及一种方法，其包括在第一和第二隔离沟槽之间的第一区域中暴露硅衬底的表面，在第一区域中蚀刻硅衬底以在第一和第二隔离沟槽之间形成凹陷， 以及通过在凹部中选择性地外延生长包含SiGe的膜来形成异质结双极晶体管的基极。

公开(公告)号：US20140151561A1

公开(公告)日：2014-06-05

申请号：US13692691

申请日：2012-12-03

Applicant: STMICROELECTRONICS S.A.

Inventor： Hani Sherry ,  Andreia Cathelin

IPC: G01J5/34

CPC classification number: G01J5/34 ,  G05F3/26 ,  H01Q1/2283 ,  H01Q7/00 ,  H03K3/0315

Abstract: A pixel circuit including: a detection circuit having first and second transistors coupled in series between differential output nodes of an antenna, wherein the antenna is configured to be sensitive to terahertz radiation; a capacitor coupled to an intermediate node between the first and second transistors; and control circuitry coupled to control nodes of the first and second transistors, the control circuitry being configured for selectively applying to the control nodes one of: a gate biasing voltage for biasing the control nodes of the first and second transistors during a detection phase of the pixel circuit; and a reset voltage for resetting a voltage stored by the capacitor.

Abstract translation: 一种像素电路，包括：检测电路，其具有串联耦合在天线的差分输出节点之间的第一和第二晶体管，其中所述天线被配置为对太赫兹辐射敏感; 耦合到第一和第二晶体管之间的中间节点的电容器; 以及耦合到所述第一和第二晶体管的控制节点的控制电路，所述控制电路被配置为向所述控制节点选择性地施加以下之一：用于在所述第一和第二晶体管的检测阶段偏置所述第一和第二晶体管的控制节点的栅极偏置电压 像素电路; 以及用于复位由电容器存储的电压的复位电压。

公开(公告)号：US08722471B2

公开(公告)日：2014-05-13

申请号：US13748126

申请日：2013-01-23

Applicant: STMicroelectronics S.A. ,  Commissariat à l'Énergie Atomique et aux

Inventor： Perrine Batude ,  Yves Morand

IPC: H01L21/00

CPC classification number: H01L21/76843 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823475

Abstract: A method for forming a via connecting a first upper level layer to a second lower level layer, both layers being surrounded with an insulating material, the method including the steps of: a) forming an opening to reach an edge of the first layer, the opening laterally continuing beyond said edge; b) forming a layer of a protection material on said edge only; c) deepening said opening by selectively etching the insulating material to reach the second lower level layer; and d) filling the opening with at least one conductive contact material.

Abstract translation: 一种用于形成连接第一上层与第二下层的通孔的方法，所述两层被绝缘材料包围，所述方法包括以下步骤：a）形成开口以到达第一层的边缘， 横向延伸超过所述边缘; b）仅在所述边缘上形成保护材料层; c）通过选择性地蚀刻绝缘材料到达第二较低层来加深所述开口; 以及d）用至少一个导电接触材料填充该开口。

公开(公告)号：US08711954B2

公开(公告)日：2014-04-29

申请号：US11966004

申请日：2007-12-28

Applicant: Arnaud Florence ,  Jerome Heurtier

Inventor： Arnaud Florence ,  Jerome Heurtier

IPC: H04B3/00

CPC classification number: H04L25/0268

Abstract: A method and a system for transferring a digital signal through a transformer, in which the current in a primary winding of the transformer is a frequency-modulated signal exhibiting sinusoidal trains of different durations according to the rising or falling edge of the digital signal to be transferred.

Abstract translation: 一种用于通过变压器传送数字信号的方法和系统，其中变压器的初级绕组中的电流是根据数字信号的上升沿或下降沿呈现不同持续时间的正弦曲线的调频信号， 转入。

公开(公告)号：US08704358B2

公开(公告)日：2014-04-22

申请号：US13688008

申请日：2012-11-28

Applicant: STMicroelectronics S.A.

Inventor： Pierre Bar ,  Sylvain Joblot ,  Nicolas Hotellier

IPC: H01L23/04

CPC classification number: H01L21/56 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/80 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/09181 ,  H01L2224/11009 ,  H01L2224/11334 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/80203 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/83203 ,  H01L2224/9202 ,  H01L2224/9222 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/80 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/81 ,  H01L2224/05552

Abstract: A method for forming an integrated circuit including the steps of: a) forming openings in a front surface of a first semiconductor wafer, the depth of the openings being smaller than 10 μm, and filling them with a conductive material; b) forming doped areas of components in active areas of the front surface, forming interconnection levels on the front surface and leveling the surface supporting the interconnection levels; c) covering with an insulating layer a front surface of a second semiconductor wafer, and leveling the surface coated with an insulator; d) applying the front surface of the second wafer coated with insulator on the front surface of the first wafer supporting interconnection levels, to obtain a bonding between the two wafers; e) forming vias from the rear surface of the second wafer, to reach the interconnection levels of the first wafer; and f) thinning the first wafer to reach the openings filled with conductive material.

Abstract translation: 一种用于形成集成电路的方法，包括以下步骤：a）在第一半导体晶片的前表面形成开口，开口深度小于10μm，并用导电材料填充; b）在前表面的有源区域中形成组分的掺杂区域，在前表面上形成互连层，并平整支撑互连层的表面; c）用绝缘层覆盖第二半导体晶片的前表面，并平整涂有绝缘体的表面; d）将涂有绝缘体的第二晶片的前表面施加在第一晶片支撑互连电平的前表面上，以获得两个晶片之间的结合; e）从第二晶片的后表面形成通孔，以达到第一晶片的互连电平; 以及f）使第一晶片变薄以到达填充有导电材料的开口。

公开(公告)号：US20140061723A1

公开(公告)日：2014-03-06

申请号：US14017024

申请日：2013-09-03

Applicant: STMicroelectronics S.A.

Inventor： Vincent Quenette

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/7851

Abstract: A MOS transistor including a U-shaped channel-forming semiconductor region and source and drain regions having the same U shape located against the channel-forming region on either side thereof, the internal surface of the channel-forming semiconductor region being coated with a conductive gate, a gate insulator being interposed.

Abstract translation: 一种MOS晶体管，包括U形沟道形成半导体区域和具有相同U形的源极和漏极区域，其位于其任一侧上的沟道形成区域，沟道形成半导体区域的内表面涂覆有导电 栅极，插入栅极绝缘体。