公开(公告)号：US20210366544A1

公开(公告)日：2021-11-25

申请号：US17394249

申请日：2021-08-04

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli HARARI

IPC: G11C16/04 ,  H01L23/528 ,  H01L27/1157 ,  G11C16/28 ,  H01L29/08 ,  H01L29/16 ,  H01L29/04 ,  H01L27/11582 ,  H01L29/06 ,  H01L29/786 ,  G11C16/10 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  H01L27/06 ,  H01L29/792 ,  H01L49/02

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

公开(公告)号：US20210313348A1

公开(公告)日：2021-10-07

申请号：US17348603

申请日：2021-06-15

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  Wu-Yi Henry Chien ,  Scott Brad Herner

IPC: H01L27/11582 ,  H01L21/768 ,  H01L21/28 ,  H01L27/1157

Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.

公开(公告)号：US20210280605A1

公开(公告)日：2021-09-09

申请号：US17329007

申请日：2021-05-24

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Chenming Hu ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11582 ,  H01L27/11568 ,  H01L21/02 ,  H01L21/28

Abstract: A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a moncrystlline semiconductor substrate.

公开(公告)号：US20210263866A1

公开(公告)日：2021-08-26

申请号：US17183154

申请日：2021-02-23

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Robert D. Norman ,  Richard S. Chernicoff ,  Eli Harari

IPC: G06F13/16 ,  G06F13/28 ,  G06F13/42

Abstract: A shared memory provides multi-channel access from multiple computing or host devices. A priority circuit prioritizes the multiple memory requests that are submitted as bids from the multiple host channels, such that those memory access requests that do not give rise to a conflict may proceed in parallel. The shared memory may be multi-ported and a routing circuit routes the prioritized memory access request to the appropriate memory ports where the allowed memory access requests may be carried out.

公开(公告)号：US20210248094A1

公开(公告)日：2021-08-12

申请号：US17169212

申请日：2021-02-05

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Robert D. Norman ,  Eli Harari ,  Khandker Nazrul Quader ,  Frank Sai-keung Lee ,  Richard S. Chernicoff ,  Youn Cheul Kim ,  Mehrdad Mofidi

IPC: G06F13/16 ,  G06F13/28 ,  G06F9/4401 ,  G06F12/0893 ,  G06F13/42 ,  G06F12/10 ,  G06F9/54 ,  H01L25/065 ,  H01L25/18

Abstract: A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.

公开(公告)号：US11069696B2

公开(公告)日：2021-07-20

申请号：US16509282

申请日：2019-07-11

Applicant: Sunrise Memory Corporation

Inventor： Eli Harari ,  Raul Adrian Cernea ,  George Samachisa ,  Wu-Yi Henry Chien

IPC: H01L27/112 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/12 ,  G11C11/56 ,  H01L27/06

Abstract: A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.

公开(公告)号：US20210210506A1

公开(公告)日：2021-07-08

申请号：US17161504

申请日：2021-01-28

Applicant: Sunrise Memory Corporation

Inventor： Tianhong Yan ,  Scott Brad Herner ,  Jie Zhou ,  Wu-Yi Henry Chien ,  Eli Harari

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L29/04 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

公开(公告)号：US11011544B2

公开(公告)日：2021-05-18

申请号：US16920603

申请日：2020-07-03

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Scott Brad Herner ,  Eli Harari

IPC: H01L27/11582 ,  H01L29/08 ,  H01L27/11568 ,  H01L27/11578 ,  H01L29/792

Abstract: A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

公开(公告)号：US10896916B2

公开(公告)日：2021-01-19

申请号：US16194225

申请日：2018-11-16

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari ,  George Samachisa ,  Yupin Fong

IPC: H01L27/11582 ,  H01L29/49 ,  H01L29/423

Abstract: A non-volatile “reverse memory cell” suitable for use as a building block for a 3-dimensional memory array includes a charge-trapping layer which is programmed or charged through gate-injection, rather than channel-injection. Such a reverse cell may be implemented as either an n-channel memory cell or a p-channel memory cell, without incurring design or process penalties, or any complexity in programming or erase operations. Furthermore, all reading, programming, erase, program-inhibiting operations may be carried out in the reverse memory cell using only positive or only negative voltages, thereby simplifying both the design and the power management operations.

公开(公告)号：US20200312416A1

公开(公告)日：2020-10-01

申请号：US16901758

申请日：2020-06-15

Applicant: SUNRISE MEMORY CORPORATION

Inventor： Eli Harari

IPC: G11C16/34 ,  H01L21/28 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  H01L29/66 ,  H01L27/06 ,  H01L29/792 ,  G11C11/56 ,  H01L27/11573 ,  H01L27/11582

Abstract: Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.