公开(公告)号：US20210366544A1

公开(公告)日：2021-11-25

申请号：US17394249

申请日：2021-08-04

申请人： SUNRISE MEMORY CORPORATION

发明人： Eli HARARI

IPC分类号： G11C16/04 ,  H01L23/528 ,  H01L27/1157 ,  G11C16/28 ,  H01L29/08 ,  H01L29/16 ,  H01L29/04 ,  H01L27/11582 ,  H01L29/06 ,  H01L29/786 ,  G11C16/10 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  H01L27/06 ,  H01L29/792 ,  H01L49/02

摘要： A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

公开(公告)号：US20230368843A1

公开(公告)日：2023-11-16

申请号：US18225879

申请日：2023-07-25

申请人： SUNRISE MEMORY CORPORATION

发明人： Eli HARARI

IPC分类号： G11C16/04 ,  H01L21/02 ,  G11C11/56 ,  G11C16/10 ,  H01L29/423 ,  H01L23/528 ,  H01L29/08 ,  H01L29/10 ,  H01L21/768 ,  H01L29/66 ,  H01L29/16 ,  H01L29/06 ,  H01L29/786 ,  H01L29/51 ,  H01L21/3213 ,  H01L29/04 ,  G11C16/34 ,  G11C16/28 ,  H01L21/28 ,  G11C16/26 ,  H01L29/792 ,  H01L27/06

CPC分类号： G11C16/0466 ,  H01L21/02164 ,  H01L21/0217 ,  G11C11/5635 ,  G11C16/0491 ,  G11C16/10 ,  H01L29/4234 ,  G11C16/0416 ,  H01L23/528 ,  H01L29/0847 ,  H01L29/1037 ,  H01L21/02532 ,  H01L21/76892 ,  H01L29/66833 ,  H01L29/16 ,  H01L29/0649 ,  H01L29/78642 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6675 ,  H01L21/02595 ,  H01L21/32133 ,  H01L28/00 ,  H10B43/10 ,  H10B43/35 ,  H01L29/04 ,  G11C16/3427 ,  H10B43/27 ,  G11C16/28 ,  G11C16/0483 ,  H01L29/40117 ,  G11C16/26 ,  H01L29/7926 ,  H10B43/40 ,  H01L27/0688 ,  G11C11/5628

摘要： A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

公开(公告)号：US20210104278A1

公开(公告)日：2021-04-08

申请号：US17121509

申请日：2020-12-14

申请人： SUNRISE MEMORY CORPORATION

发明人： Eli HARARI

IPC分类号： G11C16/04 ,  H01L23/528 ,  H01L27/1157 ,  G11C16/28 ,  H01L29/08 ,  H01L29/16 ,  H01L29/04 ,  H01L27/11582 ,  H01L29/06 ,  H01L29/786 ,  G11C16/10 ,  H01L29/10 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/11573 ,  H01L21/28 ,  G11C11/56 ,  G11C16/26 ,  G11C16/34 ,  H01L27/06 ,  H01L29/792 ,  H01L49/02

摘要： A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction. The active columns, the charge-trapping material and the conductors together form a plurality of thin film transistors, with each thin film transistor formed by one of the conductors, a portion of the lightly doped region of an active column, the charge-trapping material between the portion of the lightly doped region and the conductor, and the first and second heavily doped regions. The thin film transistors associated with each active column are organized into one or more vertical NOR strings.

公开(公告)号：US20180108423A1

公开(公告)日：2018-04-19

申请号：US15846766

申请日：2017-12-19

申请人： Sunrise Memory Corporation

发明人： Eli HARARI

IPC分类号： G11C16/34 ,  H01L29/792 ,  G11C11/56 ,  H01L29/66 ,  H01L27/06 ,  H01L21/28 ,  G11C16/28 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

CPC分类号： G11C16/3431 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3427 ,  H01L21/28282 ,  H01L27/0688 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.