公开(公告)号：US20130032876A1

公开(公告)日：2013-02-07

申请号：US13195153

申请日：2011-08-01

申请人： Kangguo CHENG ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

发明人： Kangguo CHENG ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

摘要： A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure.

摘要翻译： 晶体管结构包括设置在源极和漏极之间的沟道; 设置在所述通道上并且在所述源极和所述漏极之间的栅极导体; 以及设置在栅极导体和源极之间的栅介质层，漏极和沟道。 在晶体管结构中，源极的下部和与沟道相邻的漏极的下部设置在栅极介电层的下方并与栅极介电层接触以限定明确限定的源 - 漏扩展区。 还公开了制造晶体管结构的替代栅极方法。

公开(公告)号：US20130017667A1

公开(公告)日：2013-01-17

申请号：US13617464

申请日：2012-09-14

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Tenko Yamashita ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Tenko Yamashita ,  Ying Zhang

IPC分类号： H01L21/302

CPC分类号： H01L21/28123 ,  H01L21/76224 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203

摘要： A semiconductor device includes a substrate having at least one nitride material lined isolation cavity; and a hafnium containing dielectric fill at least partially contained in and at least partially covering at least a portion of the at least one nitride lined isolation cavity.

摘要翻译： 半导体器件包括具有至少一个氮化物材料衬里隔离腔的衬底; 以及含有铪的电介质填充物，其至少部分地包含在并且至少部分地覆盖所述至少一个氮化物衬里隔离腔的至少一部分。

公开(公告)号：US20120306015A1

公开(公告)日：2012-12-06

申请号：US13562355

申请日：2012-07-31

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong ,  Ying Zhang

IPC分类号： H01L29/78

CPC分类号： H01L29/41733 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device characterized as being an FET device structure with enlarged contact areas is disclosed. The device has a vertically recessed isolation, thereby having an exposed sidewall surface on both the source and the drain. A silicide layer is covering both the top surface and the sidewall surface of both the source and the drain. Metallic contacts to the device engage the silicide layer on its top surface and on its sidewall surface.

摘要翻译： 公开了一种特征在于具有扩大的接触面积的FET器件结构的器件。 该装置具有垂直凹入的隔离，从而在源极和漏极两者上具有暴露的侧壁表面。 硅化物层覆盖源极和漏极的顶表面和侧壁表面。 与设备的金属接触物接合在其顶表面及其侧壁表面上的硅化物层。

公开(公告)号：US20120305940A1

公开(公告)日：2012-12-06

申请号：US13151238

申请日：2011-06-01

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Bruce B. Doris ,  Lisa F. Edge ,  Keith E. Fogel ,  Johnathan E. Faltermeier ,  Jinghong Li ,  Alexander Reznicek ,  Devendra K. Sadana ,  Bin Yang

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Bruce B. Doris ,  Lisa F. Edge ,  Keith E. Fogel ,  Johnathan E. Faltermeier ,  Jinghong Li ,  Alexander Reznicek ,  Devendra K. Sadana ,  Bin Yang

IPC分类号： H01L29/24 ,  H01L21/20

CPC分类号： H01L21/02529 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

摘要： A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain.

摘要翻译： 公开了在NFET器件中的无缺陷Si：C源极/漏极的方法和结构。 接受具有{100}晶体取向的主表面的晶片。 以这样的方式在晶片中形成凹部，使得凹部的底表面和四个侧壁表面都具有{100}晶体取向。 Si：C材料在凹槽中被轴向生长，并且由于晶体取向，邻近四个侧壁表面的缺陷密度基本上与下表面相同。 外延填充的凹槽用于NFET器件的源极/漏极制造。 NFET器件沿着<100>结晶方向取向，由于源极/漏极中的缺陷Si：C，器件沟道处于拉伸应变状态。

公开(公告)号：US20120292710A1

公开(公告)日：2012-11-22

申请号：US13108138

申请日：2011-05-16

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L27/092 ,  H01L21/3205

CPC分类号： H01L21/823842 ,  H01L29/66545 ,  H01L29/7833 ,  H01L29/7843 ,  H01L2924/13085 ,  H01L2924/13092

摘要： A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.

摘要翻译： 半导体器件通过首先提供具有FET对前体的双栅极半导体器件结构形成，其包括nFET前体和pFET前体，其中nFET前体和pFET前体中的每一个包括伪栅极结构。 至少一个保护层沉积在FET对前体之间，留下伪栅极结构。 从nFET前体和pFET前体之一去除伪栅极结构，以在其中分别形成nFET栅极孔和pFET栅极孔中的一个。 填充物沉积在形成的nFET栅极孔和pFET栅极之一中。

公开(公告)号：US20120280365A1

公开(公告)日：2012-11-08

申请号：US13552296

申请日：2012-07-18

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Xuefeng Hua ,  Ying Zhang

IPC分类号： H01L29/06

CPC分类号： H01L21/308 ,  H01L21/033 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： A structure for a semiconductor device is disclosed. The structure includes a first feature and a second feature. The first feature and the second feature are formed simultaneously in a single etch process from a same monolithic substrate layer and are integrally and continuously connected to each other. The first feature has a width dimension of less than a minimum feature size achievable by lithography and the second feature has a width dimension of at least equal to a minimum feature size achievable by lithography.

摘要翻译： 公开了一种用于半导体器件的结构。 该结构包括第一特征和第二特征。 第一特征和第二特征是在相同的单片衬底层的单个蚀刻工艺中同时形成的，并且彼此一体地连续地连接。 第一特征具有小于通过光刻实现的最小特征尺寸的宽度尺寸，并且第二特征具有至少等于通过光刻实现的最小特征尺寸的宽度尺寸。

公开(公告)号：US20120267685A1

公开(公告)日：2012-10-25

申请号：US13539700

申请日：2012-07-02

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L21/823857

摘要： In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric.

摘要翻译： 在电路结构中，PFET器件具有栅极电介质，其包括高k电介质，具有金属的栅格，p源极/漏极和形成在p源极/漏极上的硅化物层; NFET器件包括栅极电介质，其包括高k电介质，具有金属的盖板，在n源极/漏极上形成的n源极/漏极和硅化物层。 外延SiGe存在于PFET栅极电介质的下面并与PFET栅极电介质直接接触，而外延SiGe不存在于NFET栅极电介质下方。

公开(公告)号：US08278175B2

公开(公告)日：2012-10-02

申请号：US12813311

申请日：2010-06-10

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L21/335

CPC分类号： H01L21/823431 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/785

摘要： Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row each having fins. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.

摘要翻译： 公开了用于制造FET器件结构的方法。 所述方法包括接收Si基材料的翅片，以及将鳍片的区域转换为氧化物元件。 氧化物元件在制造Fin-FET器件的鳍片上施加压力。 施加的压力在Fin-FET器件的器件沟道中引起压应力。 所述方法还包括接收Si基材料的矩形构件并将所述构件的区域转换为氧化物元件。 所述方法进一步包括在与N个翅片施加压力的同时被N型翅片平行地形成的构件图案化。 Fin-FET器件制造在压缩鳍片中，这导致压缩应力器件通道。 还公开了FET器件结构。 FET器件结构具有具有Si基材料的翅片的Fin-FET器件。 氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。 另外的FET器件结构具有各自具有鳍片的Fin-FET器件。 垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

公开(公告)号：US20120223386A1

公开(公告)日：2012-09-06

申请号：US13470393

申请日：2012-05-14

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/2633 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/517 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856

摘要： Asymmetric FET devices, and a method for fabricating such asymmetric devices on a fin structure is disclosed. The fabrication method includes disposing over the fin a high-k dielectric layer followed by a threshold- modifying layer, performing an ion bombardment at a tilted angle which removes the threshold-modifying layer over one of the fin's side-surfaces. The completed FET devices will be asymmetric due to the threshold-modifying layer being present only in one of two devices on the side of the fin. In an alternate embodiment further asymmetries are introduced, again using tilted ion implantation, resulting in differing gate-conductor materials for the two FinFET devices on each side of the fin.

摘要翻译： 公开了非对称FET器件，以及在翅片结构上制造这种非对称器件的方法。 该制造方法包括在散热片上布置高k电介质层，随后是阈值修饰层，以倾斜角度进行离子轰击，该倾斜角度在翅片的侧面之一上除去阈值修饰层。 完成的FET器件将是不对称的，因为阈值修饰层仅存在于翅片一侧的两个器件之一中。 在替代实施例中，引入另外的不对称性，再次使用倾斜离子注入，导致用于翅片每侧上的两个FinFET器件的不同的栅极 - 导体材料。

公开(公告)号：US08242560B2

公开(公告)日：2012-08-14

申请号：US12688347

申请日：2010-01-15

申请人： Eduard A. Cartier ,  Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

发明人： Eduard A. Cartier ,  Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A semiconductor device is provided that in one embodiment includes at least one semiconductor fin structure atop a dielectric surface, the semiconductor fin structure including a channel region of a first conductivity type and source and drain regions of a second conductivity type, in which the source and drain regions are present at opposing ends of the semiconductor fin structure. A high-k gate dielectric layer having a thickness ranging from 1.0 nm to 5.0 nm is in direct contact with the channel of the semiconductor fin structure. At least one gate conductor layer is in direct contact with the high-k gate dielectric layer. A method of forming the aforementioned device is also provided.

摘要翻译： 提供了一种半导体器件，其在一个实施例中包括在电介质表面之上的至少一个半导体鳍结构，所述半导体鳍结构包括第一导电类型的沟道区和第二导电类型的源区和漏区， 漏区存在于半导体鳍结构的相对端。 具有1.0nm至5.0nm厚度的高k栅介质层与半导体鳍结构的沟道直接接触。 至少一个栅极导体层与高k栅极电介质层直接接触。 还提供了一种形成上述装置的方法。