公开(公告)号：US11651283B1

公开(公告)日：2023-05-16

申请号：US16946672

申请日：2020-06-30

Applicant: Cadence Design Systems, Inc.

Inventor： Yong Liu ,  Ngai Ngai William Hung ,  Michael Patrick Zimmer

IPC: G06N20/00 ,  G06F17/16

CPC classification number: G06N20/00 ,  G06F17/16

Abstract: An approach is described for a method, product, and apparatus for a machine learning process using dynamic rearrangement of sparse data and corresponding weights. This approach includes a method, product, and apparatus for dynamically rearranging input data to move sparse data to a location such that computations on the sparse data might be avoided when executing a machine learning processing job. For example, sparse data within each row of the input matrix can be moved to the end of each corresponding row. When the input data is folded to fit the array, that sparse data might be at least partially contained within a fold that comprises only sparse data and possibly filler data. In such an event, computations on the fold are unnecessary and are avoided. In some embodiments, the approach includes dynamically rearranging a weight matrix to maintain a correspondence between the input data and the weights.

公开(公告)号：US11630938B1

公开(公告)日：2023-04-18

申请号：US16673792

申请日：2019-11-04

Applicant: Cadence Design Systems, Inc.

Inventor： Stefano Lorenzini ,  Antonino Armato

IPC: G06F30/398 ,  G06F11/07 ,  G05B23/02 ,  G06F11/00 ,  G06F30/394 ,  G06F11/26

Abstract: Various embodiments provide for failure mode analysis of a circuit design, which can be used as part of electronic design automation (EDA). In particular, some embodiments provide for failure mode analysis of a circuit design by determining a set of functional primitives of a circuit design component (e.g., cell at gate level) that contribute to a root cause logic for a specific failure mode.

公开(公告)号：US11620548B1

公开(公告)日：2023-04-04

申请号：US16898702

申请日：2020-06-11

Applicant: Cadence Design Systems, Inc.

Inventor： Sai Bhushan ,  Elias Lee Fallon ,  Chirag Ahuja

IPC: G06F30/3308 ,  G06F30/27 ,  G06N5/04 ,  G06N5/00 ,  G06N20/20

Abstract: The present disclosure relates to a computer-implemented method for electronic design is provided. Embodiments may include receiving, using at least one processor, an electronic design having an original schematic associated therewith and extracting one or more features for each net from the schematic. Embodiments may include storing one or more resistance or capacitance values for each net and applying the one or more resistance or capacitance values as labels for a machine learning model. Embodiments may also include training the machine learning model using one or more actual values to generate a trained model. Embodiments may further include receiving the trained model to predict parasitics for a stitching engine and generating a stitched schematic.

公开(公告)号：US11620251B2

公开(公告)日：2023-04-04

申请号：US17303230

申请日：2021-05-24

Applicant: Cadence Design Systems, Inc.

Inventor： Yao Luo

IPC: G06F13/20 ,  G06F13/42 ,  G09G5/00 ,  G06F13/40

Abstract: Methods and systems are disclosed for an upstream facing port implementation for DisplayPort link-training tunable PHY repeaters (LTTPRs). The device includes an upstream facing port to interface with an external DisplayPort source device and a downstream facing port to interface with an external DisplayPort sink device and the upstream facing port. The upstream facing port is configured to perform operations including receiving a main link data stream from an external transmitting display device, generating an outbound main link data stream, and providing the outbound main link data stream for transmitting by the external device. The device is also configured for receiving an updated main link data stream corresponding to the outbound main link data stream and sending the updated main link data stream to the downstream facing port to be transmitted to a receiving display device.

公开(公告)号：US11592482B1

公开(公告)日：2023-02-28

申请号：US17204334

申请日：2021-03-17

Applicant: Cadence Design Systems, Inc.

Inventor： Sameer Chakravarthy Chillarige ,  Anil Malik ,  Bharath Nandakumar

IPC: G01R31/3177 ,  G01R31/317

Abstract: Scan channel slicing methods and systems for testing of scan chains in an integrated circuit (IC) reduce the number of test cycles needed to effectively test all the scan chains in the IC, reducing the time and cost of testing. In scan channel slicing, rather than loading and unloading into scan chains high-power patterns having numerous switching transitions over the length of each scan chain, loading and unloading the entirety of the scan chain scan while observing it, chain load data is sliced, apportioning between the different scan chains independently observable sections (slices) of transition data in which all four bit-to-bit transitions (“0” to “0”, “0” to “1”, “1” to 0”, “1” to “1”) are ensured to exist. The remainder of the scan chain load data, which is not observed in the test procedure, can be low-transition data that consumes low dynamic power, such as mostly zeroes or mostly ones.

公开(公告)号：US11580284B1

公开(公告)日：2023-02-14

申请号：US17142360

申请日：2021-01-06

Applicant: Cadence Design Systems, Inc.

Inventor： Craig Franklin Deaton ,  Christopher William Komar ,  Lars Lundgren

IPC: G06F30/30 ,  G06F30/33 ,  G06F30/31 ,  G06F111/04 ,  G06Q10/10

Abstract: The present disclosure relates to a method for electronic circuit design. Embodiments may include receiving, using a processor, an electronic circuit design and performing a deadlock check on the electronic circuit design using a using a linear temporal logic property and a proof engine. Embodiments may further include analyzing a counterexample associated with the electronic circuit design for a loop escape condition, wherein analyzing includes proving a cover trace of a liveness obligation. If the loop escape condition is reachable from the counterexample, embodiments may include extracting one or more events associated with the loop escape condition and adding a waiver constraint to the deadlock check to force a no deadlock outcome.

公开(公告)号：US11580048B1

公开(公告)日：2023-02-14

申请号：US16356939

申请日：2019-03-18

Applicant: Cadence Design Systems, Inc.

Inventor： Thomas E. Wilson ,  Scott Huss ,  Hari Anand Ravi ,  Sachin Ramesh Gugwad ,  Balbeer Singh Rathor

IPC: G06F9/30 ,  G06F13/42 ,  G06F1/12

Abstract: Various aspects of the subject technology relate to systems, methods, and machine-readable media for DDR reference voltage training. The method includes receiving a data stream, the data stream including pulses generated from a reference voltage in relation to a voltage input logic low and a voltage input logic high of an input stream. The method also includes receiving a clock signal, the clock signal including an in-phase signal and a quadrature-phase signal, the in-phase signal orthogonal to the quadrature-phase signal. The method also includes utilizing the in-phase signal and the quadrature-phase signal of the clock signal in relation to the data stream to obtain a stream of in-phase samples and a stream of quadrature-phase samples. The method also includes adjusting the reference voltage based on a relationship of the stream of in-phase samples to the stream of quadrature-phase samples.

公开(公告)号：US11579194B1

公开(公告)日：2023-02-14

申请号：US17342764

申请日：2021-06-09

Applicant: Cadence Design Systems, Inc.

Inventor： Arvind Chokhani ,  Joseph Michael Swenton ,  Martin Thomas Amodeo

IPC: G01R31/28 ,  G06F11/00 ,  G01R31/3183 ,  G01R31/3185

Abstract: An integrated circuit (IC) test engine can generate a plurality of single cycle test patterns that target a plurality of static single cycle defects of a fabricated IC chip based on an IC design. The IC test engine can also fault simulate the plurality of single cycle test patterns against a plurality of multicycle defects in the IC design, wherein a given single cycle test pattern of the plurality of single cycle test patterns is sim-shifted to enable detection of a given multicycle fault and/or defect of the plurality of multicycle faults and/or defects.

公开(公告)号：US11574111B1

公开(公告)日：2023-02-07

申请号：US17139876

申请日：2020-12-31

Applicant: Cadence Design Systems, Inc.

Inventor： Rwik Sengupta ,  Jeffrey Nelson ,  Philippe Hurat ,  Jac Paul P. Condella

IPC: G06F30/398 ,  G06F16/532

Abstract: Disclosed are method(s), system(s), and article(s) of manufacture for implementing an approach to facilitate traceability and tamper detection of electronic designs. This approach allows for tracing and tamper detection at any stage of design and manufacturing, such as during layout generation, post-design, post-mask, and post manufacturing of the electronic designs.

公开(公告)号：US11544574B1

公开(公告)日：2023-01-03

申请号：US16522035

申请日：2019-07-25

Applicant: Cadence Design Systems, Inc.

Inventor： Wangyang Zhang ,  Elias Lee Fallon

IPC: G06N5/00 ,  G06N20/00 ,  G06F30/398

Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and optionally an electronic design layout. Embodiments may further include analyzing the electronic design schematic to determine if one or more required features of a particular circuit structure are present. If the one or more required features are present, embodiments may include analyzing, using a machine learning model, the electronic design schematic to determine if one or more optional features of the particular circuit structure are present.