公开(公告)号：US06329251B1

公开(公告)日：2001-12-11

申请号：US09636561

申请日：2000-08-10

Applicant: Cheng-Ming Wu

Inventor： Cheng-Ming Wu

IPC: H01L218234

CPC classification number: H01L21/76897 ,  H01L21/823425 ,  H01L29/41783

Abstract: Within a method for fabricating a microelectronic device there is first provided a silicon substrate. There is then formed upon the silicon substrate a first series of structures having a comparatively narrow spacing which leaves exposed a first series of comparatively narrow portions of the silicon substrate, and where the first series of structures is separated from a second series of structures also formed upon the silicon substrate, the second series of structures having a comparatively wide spacing which leaves exposed a second series of comparatively wide portions of the silicon substrate. There is then masked one of the first series of comparatively narrow portions of the silicon substrate and the second series of comparatively wide portions of the silicon substrate. There is then formed selectively upon the other of the first series of comparatively narrow portions of the silicon substrate and the second series of comparatively wide portions of the silicon substrate a series of patterned silicon layers. Finally, there is then doped simultaneously the series of patterned silicon layers and the one of the first series of comparatively narrow portions of the silicon substrate and the second series of comparatively wide portions of the silicon substrate which was masked.

Abstract translation: 在制造微电子器件的方法中，首先提供硅衬底。 然后在硅衬底上形成具有较窄间隔的第一系列结构，该第一系列结构暴露出硅衬底的第一系列相对较窄的部分，并且其中第一系列结构与也形成的第二系列结构分离 在硅衬底上，具有相对宽的间隔的第二系列结构使得暴露出硅衬底的第二系列较宽的部分。 然后，将硅衬底的第一系列相对窄的部分和硅衬底的相对较宽部分的第二系列中的一个屏蔽。 然后选择性地在硅衬底的第一系列相对较窄部分中的另一个上形成硅衬底的第二系列相对较宽的部分的一系列图案化的硅层。 最后，然后同时掺杂一系列图案化的硅层和硅衬底的第一系列比较窄的部分之一和被掩蔽的硅衬底的相对宽的部分的第二系列。

公开(公告)号：US06307213B1

公开(公告)日：2001-10-23

申请号：US09617427

申请日：2000-07-14

Applicant: Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

Inventor： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC: H01L2904

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second poly-silicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

Abstract translation: 本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。 该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。 该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。 沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。 下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。 例如，导电层可以是RAM芯片上的第一和第二多晶硅层。 然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。 然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。 该过程允许熔断器结构被建立，而不会导致熔断器损坏。 均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。

公开(公告)号：US06271570B1

公开(公告)日：2001-08-07

申请号：US09578414

申请日：2000-05-26

Applicant: Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

Inventor： Kuo Ching Huang ,  Yean-Kuen Fang ,  Mong-Song Liang ,  Jhon-Jhy Liaw ,  Cheng-Ming Wu ,  Dun-Nian Yaung

IPC: H01L2976

CPC classification number: H01L29/6659 ,  H01L21/76895 ,  H01L29/66545

Abstract: A new method of forming an improved buried contact junction is described. A gate silicon oxide layer is provided over the surface of a semiconductor substrate. A polysilicon layer is deposited overlying the gate oxide layer. A hard mask layer is deposited overlying the polysilicon layer. The hard mask and polysilicon layers are etched away where they are not covered by a mask to form a polysilicon gate electrode and interconnection lines having a silicon nitride layer thereover wherein gaps are left between the gate electrode and interconnection lines. A layer of dielectric material is deposited over the substrate to fill the gaps. The had mask layer is removed. Thereafter, the polysilicon layer is etched away where it is not covered by a buried contact mask to form an opening to the semiconductor substrate. Ions are implanted into the semiconductor substrate within the opening to form the buried contact. A tungsten layer is selectively deposited overlying the buried contact and the polysilicon gate electrode and interconnection lines to form polycide gate electrodes and interconnection lines. The dielectric material layer is anisotropically etched to leave spacers on the sidewalls of the polycide gate electrodes and interconnection lines to complete the formation of a buried contact junction in the fabrication of an integrated circuit.

Abstract translation: 描述了形成改进的埋地接触结的新方法。 在半导体衬底的表面上设置栅极氧化硅层。 沉积在栅极氧化物层上的多晶硅层。 覆盖多晶硅层的硬掩模层被沉积。 硬掩模和多晶硅层被蚀刻掉，在那里它们不被掩模覆盖以形成多晶硅栅电极和具有其上的氮化硅层的互连线，其中在栅电极和互连线之间留有间隙。 介电材料层沉积在衬底上以填充间隙。 去除了掩模层。 此后，多晶硅层被蚀刻掉，其未被掩埋的接触掩模覆盖，以形成到半导体衬底的开口。 将离子注入到开口内的半导体衬底中以形成掩埋接触。 选择性地沉积覆盖在掩埋触点和多晶硅栅电极和互连线上的钨层以形成多晶硅栅极电极和互连线。 电介质材料层被各向异性蚀刻以在多晶硅栅极电极和互连线的侧壁上留下间隔物，以在集成电路的制造中完成掩埋接触结的形成。

公开(公告)号：US6159786A

公开(公告)日：2000-12-12

申请号：US210702

申请日：1998-12-14

Applicant: Min-Hsiung Chiang ,  James Cheng-Ming Wu ,  Jenn-Ming Huang

Inventor： Min-Hsiung Chiang ,  James Cheng-Ming Wu ,  Jenn-Ming Huang

IPC: H01L21/3105 ,  H01L21/8242 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H01L27/10852 ,  H01L21/31055 ,  H01L27/10894

Abstract: A new method of maintaining good control of the dielectric thickness over a top capacitor plate during planarization by CMP by introducing a CMP stop layer under the topmost dielectric layer is described. Semiconductor device structures, including a node contact region, are provided in and on a semiconductor substrate. A bottom plate electrode is formed contacting the node contact region through an opening in a first insulating layer. A capacitor dielectric layer is deposited overlying the bottom plate electrode. A second conducting layer is deposited overlying the capacitor dielectric to form a top plate electrode of the capacitor. A second insulating layer is deposited overlying the second conducting layer. A silicon nitride polish stop layer is deposited overlying the second insulating layer. The polish stop layer, second insulating layer, second conducting layer, and capacitor dielectric layer are patterned to form the DRAM integrated circuit device. A third insulating layer is deposited overlying the first insulating layer and the polish stop layer of the DRAM integrated circuit device. The third insulating layer is planarized by chemical mechanical polishing stopping at the polish stop layer. The polish stop layer protects the top capacitor plate from damage.

Abstract translation: 描述了在通过CMP平坦化期间在顶部电容器板上保持对电介质厚度的良好控制的新方法，其中在最下面的介电层下面引入CMP停止层。 包括节点接触区域的半导体器件结构被提供在半导体衬底中和半导体衬底上。 通过第一绝缘层中的开口形成接触节点接触区域的底板电极。 电容器电介质层沉积在底板电极上。 沉积在电容器电介质上的第二导电层以形成电容器的顶板电极。 沉积在第二导电层上的第二绝缘层。 沉积覆盖在第二绝缘层上的氮化硅抛光停止层。 对抛光停止层，第二绝缘层，第二导电层和电容器电介质层进行构图以形成DRAM集成电路器件。 沉积在DRAM集成电路器件的第一绝缘层和抛光停止层上的第三绝缘层。 通过在抛光停止层处的化学机械抛光停止将第三绝缘层平坦化。 抛光停止层保护顶部电容器板免受损坏。

公开(公告)号：US6143604A

公开(公告)日：2000-11-07

申请号：US325956

申请日：1999-06-04

Applicant: Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu

Inventor： Ming-Hsiung Chiang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu

IPC: H01L21/311 ,  H01L21/60 ,  H01L21/8242

CPC classification number: H01L27/10891 ,  H01L21/76897 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/10852

Abstract: A method using a two-step contact process for making word-line strapping on DRAM devices was achieved. The method replaces a single-step contact process in which it is difficult to etch the smaller contact openings. After partially completing the DRAM cells by forming gate electrodes and word lines having a first hard mask, a planar first insulating layer is formed. Capacitor node contact openings are etched and capacitors with a protective second hard mask are completed. A thin first photoresist mask with improved resolution is used to etch small first contact openings in the first insulating layer to the word lines, while the second hard mask protects the capacitors from etching. Tungsten plugs are formed in the openings, and an interlevel dielectric layer is deposited over the capacitors. A thin second photoresist mask with improved resolution is used to etch second contact openings to the tungsten plugs. The word-line strapping for the DRAM is completed by forming tungsten plugs in the second contact openings. Since the tungsten plugs are formed after forming the capacitors, they are not subjected to high-temperature processing that could adversely affect the DRAM devices. The two thin photoresist masks replacing a thicker photoresist mask used in the single-step process allow smaller contact openings to be etched.

Abstract translation: 实现了使用两步接触工艺在DRAM器件上进行字线捆扎的方法。 该方法代替难以蚀刻较小接触开口的单步接触过程。 在通过形成具有第一硬掩模的栅电极和字线部分地完成DRAM单元之后，形成平面的第一绝缘层。 蚀刻电容器节点接触开口并完成具有保护性第二硬掩模的电容器。 使用具有改进的分辨率的薄的第一光致抗蚀剂掩模来将第一绝缘层中的小的第一接触开口蚀刻到字线，而第二硬掩模保护电容器免受蚀刻。 在开口中形成钨塞，并且在电容器上沉积层间电介质层。 使用具有改进的分辨率的薄的第二光致抗蚀剂掩模来蚀刻到钨插塞的第二接触开口。 通过在第二接触开口中形成钨插塞来完成DRAM的字线捆扎。 由于在形成电容器之后形成钨插塞，所以不会对可能对DRAM器件产生不利影响的高温处理。 替代在单步法中使用的较厚的光致抗蚀剂掩模的两个薄的光致抗蚀剂掩模允许蚀刻更小的接触开口。

公开(公告)号：US6121073A

公开(公告)日：2000-09-19

申请号：US24479

申请日：1998-02-17

Applicant: Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

Inventor： Kuo Ching Huang ,  Tse-Liang Ying ,  Cheng Yeh Shih ,  Yu Hua Lee ,  Cheng-Ming Wu

IPC: H01L23/525 ,  H01L21/82 ,  H01L27/10

CPC classification number: H01L23/5258 ,  H01L2924/0002

Abstract: This invention relates to a novel fuse structure and method for deleting redundant circuit elements on integrated circuits. This fuse structure is useful for increasing the repair yield on RAM chips by deleting defective rows of memory cells. The method involves forming a fuse area in a patterned electrically conducting layer also used to form interconnections. A relatively thin (0.4 um) insulating layer is deposited having a uniform thickness across the substrate. The next level of patterned interconnections is formed with a portion of the layer aligned over the fuse area to serve as an etch-stop layer. For example, the conducting layers can be the first and second polysilicon layers on a RAM chip. The remaining multilevel of interconnections is then formed having a number of relatively thick interlevel dielectric (ILD) layers interposed which can have an accumulative large variation in thickness across the substrate. Fuse windows (openings) are then selectively etched in the ILD layers to the etch-stop layer and the etch-stop layer is selectively etched in the fuse window to the insulating layer over the fuse area. This process allows fuse structures to be built without overetching that can cause fuse damage. The uniform thick insulating layer allows repeatable and reliable laser abrading (evaporation) to open the desired fuses.

Abstract translation: 本发明涉及一种用于删除集成电路上的冗余电路元件的新型熔丝结构和方法。 该熔丝结构可用于通过删除存储单元的有缺陷的行来增加RAM芯片的修复产量。 该方法包括在也用于形成互连的图案化导电层中形成熔丝区域。 沉积相对薄的（0.4μm）绝缘层，其跨越衬底具有均匀的厚度。 下一级图案互连形成，其中一部分层在保险丝区域上对齐以用作蚀刻停止层。 例如，导电层可以是RAM芯片上的第一和第二多晶硅层。 然后形成剩余的多层互连件，其具有插入的多个相对较厚的层间电介质层（ILD）层，其可跨越衬底具有累积的厚度变化。 然后在ILD层中选择性地将保险丝窗（开口）蚀刻到蚀刻停止层，并且将蚀刻停止层选择性地在保险丝窗口中蚀刻到保险丝区域上的绝缘层。 该过程允许熔断器结构被建立，而不会导致熔断器损坏。 均匀的厚绝缘层允许可重复且可靠的激光研磨（蒸发）来打开所需的保险丝。

公开(公告)号：US06103455A

公开(公告)日：2000-08-15

申请号：US73947

申请日：1998-05-07

Applicant: Kuo Ching Huang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

Inventor： Kuo Ching Huang ,  Wen-Chuan Chiang ,  Cheng-Ming Wu ,  Yu-Hua Lee

IPC: H01L21/768 ,  G03F7/26

CPC classification number: H01L21/76876 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7688

Abstract: A method of forming a deep contact by forming a dielectric layer 20 over a semiconductor structure 10. A main point is that the hard mask 30 is removed after the plug 52 is formed. A hard mask layer 30 is formed over the dielectric layer 20. A contact photoresist layer 36 is formed over the hard mask layer 30. The hard mask layer 30 is etched through the contact photoresist opening 39 to form a contact hard mask opening 41 exposing the dielectric layer 20. The dielectric layer 20 is etched using a high density plasma etch process using the contact photoresist layer 36 and the hard mask layer 30 as an etch mask forming a contact hole 40 in the dielectric layer 20. The contact photoresist layer 36 is removed. A metal layer 50 is formed filling the contact hole 40 and covering over the hard mask layer 30. The metal layer 50 is etched back forming a plug 52 filling the contact hole 40. Now, the hard mask layer 30 is removed. The removal of the hard mask 30 after the metal layer 50 deposition: (a) prevents the contact hole 40 from being contaminated from photoresist and other contamination formed during the hard mask 30 removal steps; and (b) creates a plug 52 that does not have a recess.

Abstract translation: 通过在半导体结构10上形成电介质层20来形成深度接触的方法。主要的一点是在形成插头52之后去除硬掩模30。 在电介质层20上形成硬掩模层30.在硬掩模层30之上形成接触光刻胶层36.硬掩模层30通过接触光致抗蚀剂开口39蚀刻以形成接触硬掩模开口41， 电介质层20.使用接触光致抗蚀剂层36和硬掩模层30作为在电介质层20中形成接触孔40的蚀刻掩模的高密度等离子体蚀刻工艺来蚀刻电介质层20.接触光致抗蚀剂层36是 删除。 形成填充接触孔40并覆盖在硬掩模层30上的金属层50.金属层50被回蚀，形成填充接触孔40的插塞52.现在，去除硬掩模层30。 在金属层50沉积之后去除硬掩模30：（a）防止接触孔40在硬掩模30去除步骤期间被光致抗蚀剂和其它污染物污染; 和（b）产生不具有凹部的插头52。

公开(公告)号：US6077738A

公开(公告)日：2000-06-20

申请号：US344398

申请日：1999-06-25

Applicant: Yu-Hua Lee ,  Cheng-Ming Wu ,  Tze-Liang Ying

Inventor： Yu-Hua Lee ,  Cheng-Ming Wu ,  Tze-Liang Ying

IPC: H01L21/02 ,  H01L21/3105 ,  H01L21/8242 ,  H01L21/20 ,  H01L27/10

CPC classification number: H01L27/10852 ,  H01L21/31053 ,  H01L27/10894 ,  H01L28/91

Abstract: A process for obtaining global planarization, or a smooth top surface topography, for an insulator layer overlying a semiconductor chip, with DRAM device structures, featuring crown shaped capacitor structures, and with peripheral, non-DRAM devices, has been developed. The process features the use of a thin silicon nitride shape, used as a hard mask, overlying insulator layers in the peripheral, non-DRAM device region, and used to prevent removal of these underlying insulator layers, during a wet etch procedure which is used to expose the vertical features of crown shaped, storage node structures, in the DRAM device region. The prevention of removal of insulator, located overlying the peripheral, non-DRAM device region, allows a subsequent, planarized, overlying insulator layer, to provide the desired smooth top surface topography for the entire semiconductor chip.

Abstract translation: 已经开发了用于获得覆盖半导体芯片的绝缘体层的全局平坦化或平滑顶表面形貌，具有冠形电容器结构的DRAM器件结构以及外围非DRAM器件的工艺。 该工艺特征在于使用薄的氮化硅形状，用作硬掩模，在外围的非DRAM器件区域中覆盖绝缘体层，并且用于在使用的湿蚀刻过程期间防止这些下面的绝缘体层的去除 以暴露在DRAM器件区域中的冠形存储节点结构的垂直特征。 防止去除位于外围非DRAM器件区域上的绝缘体，允许随后的平坦化的上覆绝缘体层为整个半导体芯片提供所需的平滑顶表面形貌。

公开(公告)号：US06015733A

公开(公告)日：2000-01-18

申请号：US133356

申请日：1998-08-13

Applicant: Yu-Hua Lee ,  James (Cheng-Ming) Wu

Inventor： Yu-Hua Lee ,  James (Cheng-Ming) Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  Y10S438/97

Abstract: A process for forming a crown shaped, polysilicon storage node structure, for a DRAM capacitor structure, has been developed. The process features the deposition of a polysilicon layer, on the top surface of a thick insulator layer, as well as on all surfaces of an opening, in the thick insulator layer. Removal of the regions of polysilicon, residing on the top surface of the thick insulator layer, results in a crown shaped, polysilicon storage node structure, in the opening, in the thick insulator layer. The crown shaped, polysilicon storage node structure, was protected from the polysilicon removal procedure, by a photoresist plug, formed overlying the polysilicon layer, in the opening, in the thick insulator layer. The photoresist plug was formed via photoresist application, exposure, and the development of exposed photoresist regions.

Abstract translation: 已经开发了用于形成用于DRAM电容器结构的冠形多晶硅存储节点结构的工艺。 该工艺的特征在于，在厚的绝缘体层中，在厚的绝缘体层的顶表面以及开口的所有表面上沉积多晶硅层。 在厚的绝缘体层中，去除驻留在厚绝缘体层的顶表面上的多晶硅区域，导致在开口中的冠状多晶硅存储节点结构。 通过在厚的绝缘体层中的开口中形成在多晶硅层上的光致抗蚀剂塞，保护了冠状多晶硅存储节点结构的多晶硅去除程序。 通过光致抗蚀剂施加，曝光和曝光的光致抗蚀剂区域的显影来形成光致抗蚀剂插塞。

公开(公告)号：US6013550A

公开(公告)日：2000-01-11

申请号：US169436

申请日：1998-10-09

Applicant: Yu-Hua Lee ,  James Cheng-Ming Wu

Inventor： Yu-Hua Lee ,  James Cheng-Ming Wu

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817 ,  Y10S438/97

Abstract: A process for forming a crown shaped storage node structure, for a DRAM capacitor structure, has been developed. The process features the patterning of a top portion, of a storage node contact plug structure, after patterning of the crown shaped storage node structure, and after removal of a silicon oxide layer, used for the definition of the crown shaped storage node structure. The sequence of patterning steps allows mis-alignment between the crown shaped storage node structure, and the underlying storage node contact hole, to occur without vulnerability to insulator layers used to passivate the transfer gate transistors, of the DRAM cell. This process also features the use of a photoresist plug, used to protect a bottom shape, of the crown shaped storage node structure during the crown shaped storage node, and the storage node contact plug structure, patterning procedures.

Abstract translation: 已经开发了用于形成用于DRAM电容器结构的冠形存储节点结构的工艺。 该方法的特征在于在图案化冠形存储节点结构之后，以及在去除用于定义冠形存储节点结构的氧化硅层之后的顶部，存储节点接触插塞结构的图案化。 图案化步骤的顺序允许在DRAM单元的绝缘体层被用来钝化传输栅极晶体管的情况下，冠状存储节点结构和下面的存储节点接触孔之间的错误对准发生。 该方法还特征在于在冠形存储节点期间使用用于保护顶部形状的顶部形状的储存节点结构的光致抗蚀剂插塞以及存储节点接触插塞结构，图案化程序。