公开(公告)号：US20070278644A1

公开(公告)日：2007-12-06

申请号：US11756403

申请日：2007-05-31

Applicant: Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

Inventor： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

IPC: H01L23/02

CPC classification number: H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/19041 ,  H05K1/186 ,  H05K3/323 ,  H05K3/4602 ,  H05K3/4614 ,  H05K2201/09536 ,  H05K2203/061 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stack structure of circuit boards embedded with semiconductor components therein is proposed, which includes at least two semiconductor components embedded circuit boards, a plurality of conductive bumps, and at least one adhesive layer. The circuit boards are each formed with a circuit layer having a plurality of electrical connection pads. The conductive bumps are formed on the electrical connection pads of at least one of the circuit boards. The adhesive layer is formed between the circuit boards such that a portion of the adhesive layer between the conductive bumps and the electrical connection pads, or between the opposing conductive bumps, forms a conductive channel and thereby forms an electrical connection between the circuit boards.

Abstract translation: 提出了嵌入其中的半导体部件的电路板的堆叠结构，其包括至少两个半导体部件嵌入式电路板，多个导电凸块和至少一个粘合剂层。 电路板各自形成有具有多个电连接焊盘的电路层。 导电凸块形成在至少一个电路板的电连接焊盘上。 粘合剂层形成在电路板之间，使得导电凸块和电连接焊盘之间或相对的导电凸块之间的粘合剂层的一部分形成导电通道，从而在电路板之间形成电连接。

公开(公告)号：US07706148B2

公开(公告)日：2010-04-27

申请号：US11588914

申请日：2006-10-27

Applicant: Shih Ping Hsu ,  Chung Cheng Lien ,  Chia Wei Chang

Inventor： Shih Ping Hsu ,  Chung Cheng Lien ,  Chia Wei Chang

IPC: H01R12/16

CPC classification number: H05K1/185 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/061 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2924/00015

Abstract: A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards.

Abstract translation: 提出了嵌入半导体芯片的电路板的堆栈结构。 提供至少两个电路板。 每个电路板包括形成在其表面上的电路层和嵌入半导体芯片的至少一个开口，其中电路层具有多个导电结构和导电焊盘，并且半导体芯片具有多个电极焊盘， 并且电路层的导电结构与半导体芯片的电极焊盘导电。 在两个电路板之间形成至少一个粘合剂层，并且设置有与电路板的导电焊盘相对应的导电材料。 因此，可以通过导电材料在电路板的导电焊盘之间形成导电路径，由此建立两个电路板之间的电连接。

公开(公告)号：US07619317B2

公开(公告)日：2009-11-17

申请号：US11984349

申请日：2007-11-16

Applicant: Chung-Cheng Lien ,  Chia-Wei Chang

Inventor： Chung-Cheng Lien ,  Chia-Wei Chang

IPC: H01L23/28 ,  H05K1/18

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3121 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/18162

Abstract: A carrier structure for a semiconductor chip and a method for manufacturing the same are disclosed. The method includes the following steps: providing a carrier board having at least one through cavity, wherein a removable film is formed on the surface of the carrier board, and a semiconductor chip is temporarily fixed in the through cavity by the removable film; filling the gap between the through cavity of the carrier board and the semiconductor chip with an adhesive material in order to fix the semiconductor chip; and removing the removable film. The disclosed method can reduce the alignment error resulted from the tiny shift of the semiconductor chip caused by jitters before the semiconductor is fixed in the cavity, thereby to increase the accuracy of the alignment, to facilitate fine wiring, and to meet the trend toward compact size of semiconductor packages.

Abstract translation: 公开了一种用于半导体芯片的载体结构及其制造方法。 该方法包括以下步骤：提供具有至少一个通孔的载体板，其中在载体板的表面上形成可移除膜，并且半导体芯片通过可移除膜临时固定在通孔中; 用粘合剂材料填充载体板的通孔和半导体芯片之间的间隙以固定半导体芯片; 并移除可拆卸胶片。 所公开的方法可以减少半导体在腔内固定之前由抖动引起的微小偏移导致的对准误差，从而提高对准的精度，以便于精细布线，并且满足紧凑的趋势 半导体封装尺寸。

公开(公告)号：US20090200658A1

公开(公告)日：2009-08-13

申请号：US12427668

申请日：2009-04-21

Applicant: Shih Ping HSU ,  Chung Cheng LIEN ,  Shang Wei CHEN

Inventor： Shih Ping HSU ,  Chung Cheng LIEN ,  Shang Wei CHEN

IPC: H01L23/12 ,  H01L23/538

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/18162 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09809 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

Abstract translation: 提出了一种嵌入半导体芯片的电路板结构。 半导体芯片被容纳在支撑板的空腔中。 在支撑板和半导体芯片上形成电介质层和电路层。 在电介质层中形成多个中空导电通孔，用于将电路层与半导体芯片电连接。 通过提供本发明的中空导电通孔，可以防止不同膨胀系数和热应力的分离结果，从而确保产品的电功能。

公开(公告)号：US20080217739A1

公开(公告)日：2008-09-11

申请号：US12153388

申请日：2008-05-19

Applicant: Chung-Cheng Lien ,  Chih-Kui Yang

Inventor： Chung-Cheng Lien ,  Chih-Kui Yang

IPC: H01L27/08

CPC classification number: H01L23/49833 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/162 ,  H05K3/0023 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09536 ,  H05K2201/09672 ,  H01L2924/00

Abstract: The present invention relates to a semiconductor packaging substrate structure with a capacitor embedded therein, which includes an inner circuit board, a patterned buffer layer, a high dielectric material layer, and a patterned metal layer. The buffer layer is disposed on at least one surface of the inner circuit board to expose the inner electrode layer of the internal board. The high dielectric material layer is located on the buffer layer and the inner electrode layer. The metal layer is placed on the high dielectric material layer including an outer circuit layer capable of electrical connection to the inner circuit layer, and an outer electrode layer corresponding to the inner electrode layer to form a capacitor. Owing to the assistance of the buffer layer, the structure can enhance the transmission and the quality of the products.

Abstract translation: 本发明涉及一种具有嵌入其中的电容器的半导体封装衬底结构，其包括内部电路板，图案化缓冲层，高介电材料层和图案化金属层。 缓冲层设置在内部电路板的至少一个表面上，以暴露内部电路板的内部电极层。 高介电材料层位于缓冲层和内电极层上。 金属层被放置在包括能够与内部电路层电连接的外部电路层的高电介质材料层和与内部电极层相对应的外部电极层以形成电容器。 由于缓冲层的帮助，该结构可以增强产品的传输和质量。

公开(公告)号：US20080029872A1

公开(公告)日：2008-02-07

申请号：US11701442

申请日：2007-02-02

Applicant: Shih-Ping Hsu ,  Chung-Cheng Lien ,  Kan-Jung Chia ,  Shang-Wei Chen

Inventor： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Kan-Jung Chia ,  Shang-Wei Chen

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L23/5389 ,  H01L24/19 ,  H01L25/105 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/18162 ,  H05K1/0306 ,  H05K1/183 ,  H05K3/02 ,  H05K3/4038 ,  H05K3/4605 ,  H05K3/4697 ,  H05K2203/0315 ,  H05K2203/1142

Abstract: A plate structure having a chip embedded therein, comprises an aluminum oxide plate having an upper surface, a lower surface, plural aluminum channels connected to the upper surface and the lower surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at least one electrode pad mounted on the active surface; and at least one build-up structure mounted on the surface of the aluminum oxide plate and the active surface of the chip, wherein the build-up structure comprises at least one conductive structure to electrically connect to the electrode pad. Besides, a method of manufacturing a plate structure having a chip embedded therein is disclosed.

Abstract translation: 具有嵌入其中的芯片的板结构包括具有上表面，下表面，连接到上表面和下表面的多个铝通道和其中的空腔的氧化铝板; 嵌入在所述腔中的芯片，其中所述芯片具有活性表面; 安装在所述有源表面上的至少一个电极焊盘; 以及至少一个堆积结构，其安装在所述氧化铝板的表面和所述芯片的有源表面上，其中所述积聚结构包括至少一个电连接到所述电极焊盘的导电结构。 此外，公开了一种制造具有嵌入其中的芯片的板结构的方法。