公开(公告)号：US07863729B2

公开(公告)日：2011-01-04

申请号：US12427668

申请日：2009-04-21

Applicant: Shih Ping Hsu ,  Chung Cheng Lien ,  Shang Wei Chen

Inventor： Shih Ping Hsu ,  Chung Cheng Lien ,  Shang Wei Chen

IPC: H01L23/12 ,  H01L23/053

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/18162 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09809 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

Abstract translation: 提出了一种嵌入半导体芯片的电路板结构。 半导体芯片被容纳在支撑板的空腔中。 在支撑板和半导体芯片上形成电介质层和电路层。 在电介质层中形成多个中空导电通孔，用于将电路层与半导体芯片电连接。 通过提供本发明的中空导电通孔，可以防止不同膨胀系数和热应力的分离结果，从而确保产品的电功能。

公开(公告)号：US07674986B2

公开(公告)日：2010-03-09

申请号：US11537417

申请日：2006-09-29

Applicant: Chia-Wei Chang ,  Chung-Cheng Lien

Inventor： Chia-Wei Chang ,  Chung-Cheng Lien

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2924/14 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/0209 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2203/061 ,  H01L2924/00

Abstract: A circuit board structure having a capacitor array and an embedded electronic component and a method for fabricating the same are proposed. Two carrier boards and a high dielectric constant material layer are provided, wherein the carrier boards have electronic components embedded therein and one surface of each carrier board has a plurality of electrode plates. The two carrier boards are laminated with the dielectric constant material layer interposed between them. The electrode plates on the surfaces of the carrier boards are opposite to each other across the high dielectric constant material layer to constitute a capacitor array. Therefore, the capacitor assembly for design of electronic devices is provided.

Abstract translation: 提出了具有电容器阵列和嵌入式电子部件的电路板结构及其制造方法。 提供了两个载体板和高介电常数材料层，其中载体板上嵌有电子部件，并且每个载体板的一个表面具有多个电极板。 将两个载板叠置在介于它们之间的介电常数材料层。 载体板表面上的电极板跨越高介电常数材料层彼此相对，以构成电容器阵列。 因此，提供了用于设计电子设备的电容器组件。

公开(公告)号：US20090091903A1

公开(公告)日：2009-04-09

申请号：US11588914

申请日：2006-10-27

Applicant: Shih Ping Hsu ,  Chung Cheng Lien ,  Chia Wei Chang

Inventor： Shih Ping Hsu ,  Chung Cheng Lien ,  Chia Wei Chang

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2203/061 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/32145 ,  H01L2924/00015

Abstract: A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards.

Abstract translation: 提出了嵌入半导体芯片的电路板的堆栈结构。 提供至少两个电路板。 每个电路板包括形成在其表面上的电路层和嵌入半导体芯片的至少一个开口，其中电路层具有多个导电结构和导电焊盘，并且半导体芯片具有多个电极焊盘， 并且电路层的导电结构与半导体芯片的电极焊盘导电。 在两个电路板之间形成至少一个粘合剂层，并且设置有与电路板的导电焊盘相对应的导电材料。 因此，可以通过导电材料在电路板的导电焊盘之间形成导电路径，由此建立两个电路板之间的电连接。

公开(公告)号：US20080210460A1

公开(公告)日：2008-09-04

申请号：US12010345

申请日：2008-01-24

Applicant: Chung-Cheng Lien ,  Chih-Kui Yang

Inventor： Chung-Cheng Lien ,  Chih-Kui Yang

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09536 ,  H05K2201/09763

Abstract: A circuit board structure with capacitors embedded therein and a method for fabricating the same are disclosed. The structure comprises at least two core layers individually comprising a dielectric layer having two opposite surfaces, circuit layers disposed on the outsides of the two opposite surfaces of the dielectric layer, and at least two capacitors embedded respectively on the insides of the two opposite surfaces of the dielectric layer and individually electrically connecting with the circuit layer at the same side; at least one adhesive layer disposed between the core layers to combine the core layers as a core structure; and at least one conductive through hole penetrating the core layers and the adhesive layer, and electrically connecting the circuit layers of the core layers. Accordingly, the present invention can improve the flexibility of circuit layout, and realize parallel connection between the capacitors to provide more capacitance.

Abstract translation: 公开了一种其中嵌有电容器的电路板结构及其制造方法。 该结构包括至少两个核心层，其单独地包括具有两个相对表面的电介质层，设置在电介质层的两个相对表面的外侧的电路层，以及分别嵌入在介电层的两个相对表面的内部的内部的至少两个电容器 所述电介质层与所述电路层在同一侧分别电连接; 设置在所述芯层之间的至少一个粘合剂层，以将所述芯层组合为芯结构; 以及穿透芯层和粘合剂层的至少一个导电通孔，并且电连接芯层的电路层。 因此，本发明可以提高电路布局的灵活性，并且实现电容器之间的并联以提供更多的电容。

公开(公告)号：US20070181995A1

公开(公告)日：2007-08-09

申请号：US11544199

申请日：2006-10-05

Applicant: Shih Ping Hsu ,  Chung Cheng Lien ,  Shang Wei Chen

Inventor： Shih Ping Hsu ,  Chung Cheng Lien ,  Shang Wei Chen

IPC: H01L23/12

CPC classification number: H01L23/5389 ,  H01L23/13 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/24 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/24227 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/18162 ,  H01L2924/351 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09809 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A circuit board structure embedded with semiconductor chips is proposed. A semiconductor chip is received in a cavity of a supporting board. A dielectric layer and a circuit layer are formed on the supporting board and the semiconductor chip. A plurality of hollow conductive vias are formed in the dielectric layer for electrically connecting the circuit layer to the semiconductor chip. By providing the hollow conductive vias of present invention, the separating results of different coefficients of expansion and thermal stress are prevented, and thus electrical function of products is ensured.

Abstract translation: 提出了一种嵌入半导体芯片的电路板结构。 半导体芯片被容纳在支撑板的空腔中。 在支撑板和半导体芯片上形成电介质层和电路层。 在电介质层中形成多个中空导电通孔，用于将电路层与半导体芯片电连接。 通过提供本发明的中空导电通孔，可以防止不同膨胀系数和热应力的分离结果，从而确保产品的电功能。

公开(公告)号：US20070147014A1

公开(公告)日：2007-06-28

申请号：US11537417

申请日：2006-09-29

Applicant: Chia-Wei Chang ,  Chung-Cheng Lien

Inventor： Chia-Wei Chang ,  Chung-Cheng Lien

IPC: H05K7/00

CPC classification number: H05K1/162 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2924/14 ,  H05K1/185 ,  H05K3/4602 ,  H05K3/4626 ,  H05K2201/0209 ,  H05K2201/09536 ,  H05K2201/09672 ,  H05K2203/061 ,  H01L2924/00

Abstract: A circuit board structure having a capacitor array and an embedded electronic component and a method for fabricating the same are proposed. Two carrier boards and a high dielectric constant material layer are provided, wherein the carrier boards have electronic components embedded therein and one surface of each carrier board has a plurality of electrode plates. The two carrier boards are laminated with the dielectric constant material layer interposed between them. The electrode plates on the surfaces of the carrier boards are opposite to each other across the high dielectric constant material layer to constitute a capacitor array. Therefore, the capacitor assembly for design of electronic devices is provided.

Abstract translation: 提出了具有电容器阵列和嵌入式电子部件的电路板结构及其制造方法。 提供了两个载体板和高介电常数材料层，其中载体板上嵌有电子部件，并且每个载体板的一个表面具有多个电极板。 将两个载板叠置在介于它们之间的介电常数材料层。 载体板表面上的电极板跨越高介电常数材料层彼此相对，以构成电容器阵列。 因此，提供了用于设计电子设备的电容器组件。

公开(公告)号：US07656040B2

公开(公告)日：2010-02-02

申请号：US11756403

申请日：2007-05-31

Applicant: Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

Inventor： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/82 ,  H01L25/105 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/19041 ,  H05K1/186 ,  H05K3/323 ,  H05K3/4602 ,  H05K3/4614 ,  H05K2201/09536 ,  H05K2203/061 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A stack structure of circuit boards embedded with semiconductor components therein is proposed, which includes at least two semiconductor components embedded circuit boards, a plurality of conductive bumps, and at least one adhesive layer. The circuit boards are each formed with a circuit layer having a plurality of electrical connection pads. The conductive bumps are formed on the electrical connection pads of at least one of the circuit boards. The adhesive layer is formed between the circuit boards such that a portion of the adhesive layer between the conductive bumps and the electrical connection pads, or between the opposing conductive bumps, forms a conductive channel and thereby forms an electrical connection between the circuit boards.

Abstract translation: 提出了嵌入其中的半导体部件的电路板的堆叠结构，其包括至少两个半导体部件嵌入式电路板，多个导电凸块和至少一个粘合剂层。 电路板各自形成有具有多个电连接焊盘的电路层。 导电凸块形成在至少一个电路板的电连接焊盘上。 粘合剂层形成在电路板之间，使得导电凸块和电连接焊盘之间或相对的导电凸块之间的粘合剂层的一部分形成导电通道，从而在电路板之间形成电连接。

公开(公告)号：US20080308309A1

公开(公告)日：2008-12-18

申请号：US11808962

申请日：2007-06-14

Applicant: Chung-Cheng Lien ,  Chih-Kui Yang

Inventor： Chung-Cheng Lien ,  Chih-Kui Yang

IPC: H05K1/16 ,  H05K3/10

CPC classification number: H05K1/162 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2203/0152 ,  H05K2203/0353 ,  H05K2203/0376 ,  H05K2203/0537 ,  H05K2203/1131 ,  Y10T29/49155

Abstract: A structure of a packaging substrate having capacitors embedded therein is disclosed. The structure comprises a core substrate, a dielectric layer, and an outer circuit layer. The core substrate comprises an inner circuit layer. The dielectric layer is disposed at both sides of the core substrate, having first conductive vias each connecting to the inner circuit layer through a piece of outer electrode plate, a piece of high dielectric material layer, a piece of inner electrode plate, and a piece of adhesive layer, in sequence. The outer circuit layer is disposed on the surface of each of the dielectric layers. Herein, the capacitor is composed of a piece of the outer electrode plate, the high dielectric material layer and the inner electrode plate. The invention further comprises a method for manufacturing the same. This can achieve low costs, avoid the formation of voids, and reduce parasitic capacitance.

Abstract translation: 公开了一种其中嵌有电容器的封装衬底的结构。 该结构包括芯基板，电介质层和外电路层。 芯基板包括内电路层。 电介质层设置在芯基板的两侧，具有通过一片外电极板，一片高电介质材料层，一片内电极板和一片连接到内电路层的第一导电通孔 的粘合剂层。 外电路层设置在每个电介质层的表面上。 这里，电容器由外电极板，高介电材料层和内电极板构成。 本发明还包括其制造方法。 这可以实现低成本，避免形成空隙，并减少寄生电容。

公开(公告)号：US20080237833A1

公开(公告)日：2008-10-02

申请号：US12047851

申请日：2008-03-13

Applicant: Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

Inventor： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

IPC: H01L23/49

CPC classification number: H01L21/6835 ,  H01L21/568 ,  H01L24/27 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81801 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multi-chip semiconductor package structure is disclosed according to the present invention. The package structure includes: a carrier board having a first surface, a second surface, and at least one opening penetrating the first and second surfaces, the first and second surfaces each being formed with a plurality of electrically connecting pads thereon; a semiconductor component received in the opening and having first and second active surfaces, the first and second active surfaces each being formed with a plurality of electrode pads thereon; a plurality of first conductive elements electrically connected to the electrically connecting pads on the second surface of the carrier board and the electrode pads on the second active surface of the semiconductor component; a semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads electrically connected to the electrically connecting pads on the first surface of the carrier board and the electrode pads on the first active surface of the semiconductor component; and a molding material formed on a portion of the second surface of the carrier board and the second active surface of the semiconductor component to cover the first conductive elements. The present invention provides a modularized structure capable of electrically connecting to other modules or stacked devices as well as enhancing electrical performance.

Abstract translation: 根据本发明公开了一种多芯片半导体封装结构。 封装结构包括：承载板，具有第一表面，第二表面和穿过第一表面和第二表面的至少一个开口，第一和第二表面各自在其上形成有多个电连接焊盘; 半导体元件，其接收在所述开口中并且具有第一和第二有源表面，所述第一和第二有源表面各自在其上形成有多个电极焊盘; 电连接到载板的第二表面上的电连接焊盘和半导体部件的第二有源表面上的电极焊盘的多个第一导电元件; 具有活性表面和非活性表面的半导体芯片，所述活性表面具有电连接到所述载体板的第一表面上的电连接焊盘和所述半导体部件的第一有源表面上的电极焊盘的多个电极焊盘; 以及模制材料，其形成在所述载板的所述第二表面的一部分和所述半导体部件的所述第二有源表面上以覆盖所述第一导电元件。 本发明提供一种能够电连接到其他模块或堆叠装置以及增强电性能的模块化结构。

公开(公告)号：US20080237832A1

公开(公告)日：2008-10-02

申请号：US12047810

申请日：2008-03-13

Applicant: Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

Inventor： Shih-Ping Hsu ,  Chung-Cheng Lien ,  Chia-Wei Chang

IPC: H01L23/49

CPC classification number: H01L25/0657 ,  H01L24/16 ,  H01L25/03 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A multi-chip semiconductor package structure is disclosed, including a carrier board having a first and an opposing second surfaces and formed with at least an opening penetrating the first and second surfaces, wherein a plurality of electrically connecting pads are formed on the first and second surfaces of the carrier board, respectively; a semiconductor component disposed in the opening, the semiconductor component having a first and a second active surfaces each with a plurality of electrode pads being formed thereon; a third semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for electrically connecting with the electrically connecting pads on the first surface of the carrier board and the electrode pads on the first active surface of the semiconductor component; and a fourth semiconductor chip having an active surface and an inactive surface, the active surface having a plurality of electrode pads formed thereon for electrically connecting with the electrically connecting pads on the second surface of the carrier board and the electrode pads on the second active surface of the semiconductor component, thereby providing a modularized structure for electrically connecting with other modules or stack devices and enhancing electrical functionality.

Abstract translation: 公开了一种多芯片半导体封装结构，其包括具有第一和相对的第二表面的载体板，并形成有至少一个贯穿第一和第二表面的开口，其中多个电连接焊盘形成在第一和第二表面上 分别为载板的表面; 设置在所述开口中的半导体部件，所述半导体部件具有在其上形成有多个电极焊盘的第一和第二有源面; 具有活性表面和非活性表面的第三半导体芯片，所述活性表面具有形成在其上的多个电极焊盘，用于与载体板的第一表面上的电连接焊盘和第一有源表面上的电极焊盘电连接 半导体元件; 以及具有活性表面和非活性表面的第四半导体芯片，所述活性表面具有形成在其上的多个电极焊盘，用于与所述载体板的第二表面上的电连接焊盘和所述第二有源表面上的电极焊盘电连接 从而提供用于与其他模块或堆叠装置电连接并增强电功能性的模块化结构。