Delay cell and phase locked loop using the same
    31.
    发明申请
    Delay cell and phase locked loop using the same 有权
    延迟单元和锁相环使用相同

    公开(公告)号:US20080238502A1

    公开(公告)日:2008-10-02

    申请号:US12003676

    申请日:2007-12-31

    Abstract: A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

    Abstract translation: 通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环,从而提高内部时钟的抖动特性。 延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器,以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。 锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器,用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器 响应于控制电压和一个或多个频率范围控制信号,其中使用内部时钟产生反馈时钟。

    Semiconductor memory devices and a method thereof
    32.
    发明申请
    Semiconductor memory devices and a method thereof 有权
    半导体存储器件及其方法

    公开(公告)号:US20080151635A1

    公开(公告)日:2008-06-26

    申请号:US11892461

    申请日:2007-08-23

    CPC classification number: G11C16/28 G11C7/08 G11C7/14

    Abstract: Semiconductor memory devices and a method thereof are provided. An example semiconductor memory device may include a control signal generation unit configured to generate a plurality of control signals in response to a bias current, a reference current generation unit configured to generate a reference current in response to the plurality of control signals and a sense amplifier configured to sense and amplify data stored in a given memory cell based on the reference current and a current on a bit line connected to the memory cell. Another example semiconductor memory device may include a memory bank including a plurality of memory cells and a sense amplifier bank including a plurality of sense amplifier units sharing a common line, each of the sense amplifier units including a current source configured to form a current path between the common line and a first voltage supply in response to an enable signal and a gating signal and a sense amplifier configured to sense and amplify data stored in a corresponding memory cell among the plurality of memory cells based on a signal on a bit line connected with the corresponding memory cell and a signal on the common line.

    Abstract translation: 提供半导体存储器件及其方法。 示例性半导体存储器件可以包括:控制信号生成单元,被配置为响应于偏置电流产生多个控制信号;参考电流产生单元,被配置为响应于所述多个控制信号产生参考电流;以及读出放大器 被配置为基于所述参考电流和连接到所述存储器单元的位线上的电流来感测和放大存储在给定存储器单元中的数据。 另一示例性半导体存储器件可以包括存储器组,其包括多个存储器单元和包括共享公共线的多个读出放大器单元的读出放大器组,每个读出放大器单元包括被配置为形成电流源 所述公共线路和第一电压电源响应于使能信号和门控信号,以及读出放大器,被配置为基于与所述多个存储器单元中的位线相关联的信号来感测和放大存储在所述多个存储器单元中的相应存储器单元中的数据 相应的存储单元和公共线上的信号。

    VOLTAGE REGULATOR FOR USE IN NONVOLATILE SEMICONDUCTOR MEMORY
    33.
    发明申请
    VOLTAGE REGULATOR FOR USE IN NONVOLATILE SEMICONDUCTOR MEMORY 有权
    用于非线性半导体存储器的电压调节器

    公开(公告)号:US20080150499A1

    公开(公告)日:2008-06-26

    申请号:US11844508

    申请日:2007-08-24

    CPC classification number: G11C16/30 G11C5/147

    Abstract: The invention relates to a voltage regulator for operation of a semiconductor memory device. In embodiments, the voltage regulator includes a standby regulator unit and an active regulating unit. Embodiments of the invention decouple the operation of the standby regulating unit and the active regulating unit of a voltage regulator so that both can operate simultaneously, for example during a read operation. In embodiments of the invention, the standby regulating unit includes a short pulse generator and a feedback loop to disable the standby regulating unit for a predetermined amount of time.

    Abstract translation: 本发明涉及用于半导体存储器件操作的电压调节器。 在实施例中,电压调节器包括备用调节器单元和主动调节单元。 本发明的实施例解除了电压调节器的待机调节单元和有源调节单元的操作,使得两者可以同时操作,例如在读取操作期间。 在本发明的实施例中,待机调节单元包括短脉冲发生器和反馈回路,以使待机调节单元停止预定的时间量。

    Dishwasher
    34.
    发明申请
    Dishwasher 失效
    洗碗机

    公开(公告)号:US20070261725A1

    公开(公告)日:2007-11-15

    申请号:US10554864

    申请日:2005-09-15

    CPC classification number: A47L15/4204 A47L15/4225 A47L15/4227

    Abstract: The present invention relates to a dishwasher. In more detail, the present invention provides a dishwasher including a sump housing for holding washing water, a washing water pumping unit for pumping the washing water, a drain chamber for receiving the washing water pumped thus, a soil chamber for receiving the washing water through the drain chamber, a guide assembly for guiding the washing water pumped thus to be provided to the soil chamber via the drain chamber, and a sump cover covered on an upper surface of the sump housing for filtering the washing water overflowed from the soil chamber, thereby filtering the washing water effectively, and improving recovery ratio of the washing water to reduce consumption of the washing water and power.

    Abstract translation: 洗碗机技术领域本发明涉及一种洗碗机。 更详细地说,本发明提供了一种洗碗机,其包括用于保持洗涤水的贮槽壳体,用于泵送洗涤水的洗涤水泵送单元,用于接收由此泵送的洗涤水的排水室,用于接收洗涤水的污物室 排水室,引导组件,用于引导被泵送的洗涤水,以通过排放室提供给土壤室;以及贮槽盖,其覆盖在贮槽壳体的上表面上,用于过滤从污物室溢出的洗涤水, 有效地过滤洗涤水,提高洗涤水的回收率,降低洗涤水的消耗和电力。

    NOR flash memory and related read method
    35.
    发明申请
    NOR flash memory and related read method 有权
    NOR闪存及相关读取方式

    公开(公告)号:US20070171723A1

    公开(公告)日:2007-07-26

    申请号:US11606029

    申请日:2006-11-30

    CPC classification number: G11C16/26

    Abstract: A NOR flash memory is disclosed including a memory cell, sense amplifier output driver, and control circuit. A sense period for a sense operation performed by the sense amplifier is made synchronous with a clock signal so as to avoid power supply or ground signal noise generated by operation of the output driver.

    Abstract translation: 公开了一种NOR闪存,其包括存储单元,读出放大器输出驱动器和控制电路。 由读出放大器执行的感测操作的感测周期与时钟信号同步,以避免由输出驱动器的操作产生的电源或接地信号噪声。

    On die termination circuit
    36.
    发明授权
    On die termination circuit 有权
    在芯片终端电路上

    公开(公告)号:US07208973B2

    公开(公告)日:2007-04-24

    申请号:US11008043

    申请日:2004-12-09

    Applicant: Dae Han Kwon

    Inventor: Dae Han Kwon

    CPC classification number: H04L25/0278

    Abstract: The present invention discloses an on die termination circuit. The on die termination circuit used in a DDR2 employs transmission gates as pull-up and pull-down switches, equalizes pull-up and pull-down resistance values by changing connection relations between switches and resistors, and maintains a constant voltage of an input pin.

    Abstract translation: 本发明公开了一种片上终端电路。 DDR2中使用的裸片终端电路使用传输门作为上拉和下拉开关,通过改变开关和电阻之间的连接关系来平衡上拉和下拉电阻值,并保持输入引脚的恒定电压 。

    Flash memory device and voltage generating circuit for the same
    37.
    发明申请
    Flash memory device and voltage generating circuit for the same 有权
    闪存器件和电压发生电路相同

    公开(公告)号:US20070081392A1

    公开(公告)日:2007-04-12

    申请号:US11521479

    申请日:2006-09-15

    CPC classification number: G11C8/08 G11C11/5621 G11C16/30

    Abstract: A flash memory device includes a memory cell array including a plurality of memory cells. The flash memory device also includes a voltage generating circuit which generates a plurality of constant voltages to be applied to the memory cell array, the voltage generating circuit including a plurality of voltage regulators which generate at least two constant voltages, each having a constant voltage difference.

    Abstract translation: 闪存器件包括包括多个存储单元的存储单元阵列。 闪速存储装置还包括产生要施加到存储单元阵列的多个恒定电压的电压产生电路,该电压产生电路包括产生至少两个恒定电压的多个电压调节器,每个恒定电压具有恒定的电压差 。

    Dishwasher
    39.
    发明申请
    Dishwasher 审中-公开
    洗碗机

    公开(公告)号:US20060060227A1

    公开(公告)日:2006-03-23

    申请号:US11094500

    申请日:2005-03-31

    CPC classification number: A47L15/4204 A47L15/4225

    Abstract: Provided is a dishwasher having an improved structure. The dishwasher includes a sump for collecting washing water for washing a contaminated dish, and a main motor for circulating the washing water collected in the sump. Furthermore, the dishwasher includes a washing pump having an impeller connected with the main motor to pump the washing water, and a discharge pump disposed at a predetermined portion of the sump for discharging the washing water. Also in the dishwasher, a lower housing having a contaminant chamber is disposed on a substantially same plane as the impeller for filtering some of the washing water. According to the present invention, the dishwasher can increase the dishwashing space and discharge contaminant in an inside of the dishwasher with ease.

    Abstract translation: 提供一种具有改进结构的洗碗机。 洗碗机包括用于收集用于洗涤污染盘的洗涤水的贮槽和用于使收集在贮槽中的洗涤水循环的主马达。 此外,洗碗机包括具有与主马达连接的叶轮以泵送洗涤水的洗涤泵,以及设置在贮槽的预定部分以排出洗涤水的排出泵。 同样在洗碗机中,具有污染物室的下壳体设置在与用于过滤一些洗涤水的叶轮大致相同的平面上。 根据本发明,洗碗机可以容易地增加餐具洗涤空间并排出洗碗机内部的污染物。

    Dishwasher
    40.
    发明申请
    Dishwasher 审中-公开
    洗碗机

    公开(公告)号:US20060054195A1

    公开(公告)日:2006-03-16

    申请号:US11055624

    申请日:2005-02-11

    CPC classification number: A47L15/4246

    Abstract: A dishwasher for completely collecting used wash water into a sump is disclosed, the dishwasher including a housing; a tub provided in the housing and receiving dishes to be washed; a sump provided at the tub so as to receive wash water and including an upper end configured not to protrude from a bottom surface of the tub; and a sprayer mounted in the tub so as to spray the wash water of the sump on the dishes.

    Abstract translation: 公开了一种用于将二手洗涤水完全收集到贮槽中的洗碗机,洗碗机包括壳体; 设置在所述外壳中并容纳要洗涤的餐具的浴缸; 设置在所述桶中以便接收洗涤水并包括构造成不从所述桶的底表面突出的上端的贮槽; 以及安装在浴缸中的喷雾器,以将贮槽上的洗涤水喷洒在盘子上。

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